2011-12-05 08:58:01 +00:00
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// Copyright 2011 the V8 project authors. All rights reserved.
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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// * Neither the name of Google Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#include <stdlib.h>
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2019-05-24 13:51:59 +00:00
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#include "src/init/v8.h"
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2014-06-03 08:12:43 +00:00
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2019-05-21 09:30:15 +00:00
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#include "src/codegen/code-factory.h"
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#include "src/codegen/macro-assembler.h"
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2015-07-31 11:07:50 +00:00
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#include "src/debug/debug.h"
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2019-05-20 09:15:06 +00:00
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#include "src/diagnostics/disasm.h"
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#include "src/diagnostics/disassembler.h"
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2019-05-22 07:55:37 +00:00
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#include "src/execution/frames-inl.h"
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2019-05-23 13:27:57 +00:00
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#include "src/utils/ostreams.h"
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2019-05-23 08:51:46 +00:00
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#include "src/objects/objects-inl.h"
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2014-06-03 08:12:43 +00:00
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#include "test/cctest/cctest.h"
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2011-12-05 08:58:01 +00:00
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2017-08-11 11:22:28 +00:00
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namespace v8 {
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namespace internal {
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2011-12-05 08:58:01 +00:00
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#define __ assm.
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TEST(DisasmX64) {
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2013-04-10 08:29:39 +00:00
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CcTest::InitializeVM();
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2014-03-05 09:28:26 +00:00
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Isolate* isolate = CcTest::i_isolate();
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HandleScope scope(isolate);
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2016-09-12 06:24:06 +00:00
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v8::internal::byte buffer[8192];
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2019-01-16 18:29:52 +00:00
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Assembler assm(AssemblerOptions{},
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ExternalAssemblerBuffer(buffer, sizeof buffer));
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2011-12-05 08:58:01 +00:00
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// Short immediate instructions
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__ addq(rax, Immediate(12345678));
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2014-03-26 12:15:35 +00:00
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__ orq(rax, Immediate(12345678));
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2011-12-05 08:58:01 +00:00
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__ subq(rax, Immediate(12345678));
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2014-03-26 12:15:35 +00:00
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__ xorq(rax, Immediate(12345678));
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__ andq(rax, Immediate(12345678));
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2011-12-05 08:58:01 +00:00
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// ---- This one caused crash
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__ movq(rbx, Operand(rsp, rcx, times_2, 0)); // [rsp+rcx*4]
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// ---- All instructions that I can think of
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__ addq(rdx, rbx);
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__ addq(rdx, Operand(rbx, 0));
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__ addq(rdx, Operand(rbx, 16));
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__ addq(rdx, Operand(rbx, 1999));
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2014-03-05 09:28:26 +00:00
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__ addq(rdx, Operand(rbx, -4));
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__ addq(rdx, Operand(rbx, -1999));
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2011-12-05 08:58:01 +00:00
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__ addq(rdx, Operand(rsp, 0));
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__ addq(rdx, Operand(rsp, 16));
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__ addq(rdx, Operand(rsp, 1999));
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2014-03-05 09:28:26 +00:00
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__ addq(rdx, Operand(rsp, -4));
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__ addq(rdx, Operand(rsp, -1999));
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__ nop();
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__ addq(rsi, Operand(rcx, times_4, 0));
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__ addq(rsi, Operand(rcx, times_4, 24));
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__ addq(rsi, Operand(rcx, times_4, -4));
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__ addq(rsi, Operand(rcx, times_4, -1999));
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2011-12-05 08:58:01 +00:00
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__ nop();
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__ addq(rdi, Operand(rbp, rcx, times_4, 0));
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__ addq(rdi, Operand(rbp, rcx, times_4, 12));
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2014-03-05 09:28:26 +00:00
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__ addq(rdi, Operand(rbp, rcx, times_4, -8));
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__ addq(rdi, Operand(rbp, rcx, times_4, -3999));
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2011-12-05 08:58:01 +00:00
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__ addq(Operand(rbp, rcx, times_4, 12), Immediate(12));
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2018-08-14 08:39:05 +00:00
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__ bswapl(rax);
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__ bswapq(rdi);
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2015-03-20 08:37:20 +00:00
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__ bsrl(rax, r15);
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__ bsrl(r9, Operand(rcx, times_8, 91919));
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2011-12-05 08:58:01 +00:00
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__ nop();
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__ addq(rbx, Immediate(12));
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__ nop();
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__ nop();
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2014-03-26 12:15:35 +00:00
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__ andq(rdx, Immediate(3));
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__ andq(rdx, Operand(rsp, 4));
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2011-12-05 08:58:01 +00:00
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__ cmpq(rdx, Immediate(3));
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__ cmpq(rdx, Operand(rsp, 4));
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__ cmpq(Operand(rbp, rcx, times_4, 0), Immediate(1000));
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__ cmpb(rbx, Operand(rbp, rcx, times_2, 0));
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__ cmpb(Operand(rbp, rcx, times_2, 0), rbx);
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2014-03-26 12:15:35 +00:00
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__ orq(rdx, Immediate(3));
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__ xorq(rdx, Immediate(3));
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2011-12-05 08:58:01 +00:00
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__ nop();
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2013-11-18 15:24:41 +00:00
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__ cpuid();
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2014-04-11 06:32:06 +00:00
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__ movsxbl(rdx, Operand(rcx, 0));
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2011-12-05 08:58:01 +00:00
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__ movsxbq(rdx, Operand(rcx, 0));
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2014-04-11 06:32:06 +00:00
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__ movsxwl(rdx, Operand(rcx, 0));
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2011-12-05 08:58:01 +00:00
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__ movsxwq(rdx, Operand(rcx, 0));
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__ movzxbl(rdx, Operand(rcx, 0));
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__ movzxwl(rdx, Operand(rcx, 0));
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__ movzxbq(rdx, Operand(rcx, 0));
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__ movzxwq(rdx, Operand(rcx, 0));
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__ nop();
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2014-03-21 02:42:10 +00:00
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__ imulq(rdx, rcx);
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2011-12-05 08:58:01 +00:00
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__ shld(rdx, rcx);
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__ shrd(rdx, rcx);
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2014-10-02 09:08:09 +00:00
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__ shlq(Operand(rdi, rax, times_4, 100), Immediate(1));
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__ shlq(Operand(rdi, rax, times_4, 100), Immediate(6));
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__ shlq(Operand(r15, 0), Immediate(1));
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__ shlq(Operand(r15, 0), Immediate(6));
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__ shlq_cl(Operand(r15, 0));
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__ shlq_cl(Operand(r15, 0));
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__ shlq_cl(Operand(rdi, rax, times_4, 100));
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__ shlq_cl(Operand(rdi, rax, times_4, 100));
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__ shlq(rdx, Immediate(1));
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__ shlq(rdx, Immediate(6));
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__ shll(Operand(rdi, rax, times_4, 100), Immediate(1));
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__ shll(Operand(rdi, rax, times_4, 100), Immediate(6));
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__ shll(Operand(r15, 0), Immediate(1));
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__ shll(Operand(r15, 0), Immediate(6));
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__ shll_cl(Operand(r15, 0));
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__ shll_cl(Operand(r15, 0));
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__ shll_cl(Operand(rdi, rax, times_4, 100));
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__ shll_cl(Operand(rdi, rax, times_4, 100));
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__ shll(rdx, Immediate(1));
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__ shll(rdx, Immediate(6));
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2018-09-12 07:29:11 +00:00
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__ btq(Operand(rdx, 0), rcx);
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__ btsq(Operand(rdx, 0), rcx);
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__ btsq(Operand(rbx, rcx, times_4, 0), rcx);
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__ btsq(rcx, Immediate(13));
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__ btrq(rcx, Immediate(13));
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2011-12-05 08:58:01 +00:00
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__ nop();
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2014-03-19 08:59:04 +00:00
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__ pushq(Immediate(12));
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__ pushq(Immediate(23456));
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__ pushq(rcx);
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__ pushq(rsi);
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2019-10-24 14:49:31 +00:00
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__ pushq(Operand(rbp, StandardFrameConstants::kFunctionOffset));
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2014-03-19 08:59:04 +00:00
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__ pushq(Operand(rbx, rcx, times_4, 0));
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__ pushq(Operand(rbx, rcx, times_4, 0));
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__ pushq(Operand(rbx, rcx, times_4, 10000));
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__ popq(rdx);
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__ popq(rax);
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__ popq(Operand(rbx, rcx, times_4, 0));
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2011-12-05 08:58:01 +00:00
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__ nop();
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__ addq(rdx, Operand(rsp, 16));
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__ addq(rdx, rcx);
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__ movb(rdx, Operand(rcx, 0));
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__ movb(rcx, Immediate(6));
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__ movb(Operand(rsp, 16), rdx);
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__ movw(Operand(rsp, 16), rdx);
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__ nop();
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__ movsxwq(rdx, Operand(rsp, 12));
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__ movsxbq(rdx, Operand(rsp, 12));
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__ movsxlq(rdx, Operand(rsp, 12));
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__ movzxwq(rdx, Operand(rsp, 12));
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__ movzxbq(rdx, Operand(rsp, 12));
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__ nop();
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__ movq(rdx, Immediate(1234567));
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__ movq(rdx, Operand(rsp, 12));
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__ movq(Operand(rbx, rcx, times_4, 10000), Immediate(12345));
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__ movq(Operand(rbx, rcx, times_4, 10000), rdx);
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__ nop();
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__ decb(rdx);
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__ decb(Operand(rax, 10));
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__ decb(Operand(rbx, rcx, times_4, 10000));
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__ decq(rdx);
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__ cdq();
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2019-12-04 09:15:26 +00:00
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__ repstosl();
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2019-10-15 08:17:25 +00:00
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__ repstosq();
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2011-12-05 08:58:01 +00:00
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__ nop();
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__ idivq(rdx);
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2014-11-03 10:04:37 +00:00
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__ mull(rdx);
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__ mulq(rdx);
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2020-01-24 17:08:27 +00:00
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__ negb(rdx);
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__ negb(r10);
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__ negw(rdx);
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__ negl(rdx);
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2014-03-26 01:13:09 +00:00
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__ negq(rdx);
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2020-01-24 17:08:27 +00:00
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__ negb(Operand(rsp, 12));
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__ negw(Operand(rsp, 12));
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__ negl(Operand(rsp, 12));
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__ negb(Operand(rsp, 12));
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2014-03-26 12:15:35 +00:00
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__ notq(rdx);
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2011-12-05 08:58:01 +00:00
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__ testq(Operand(rbx, rcx, times_4, 10000), rdx);
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2014-03-21 02:42:10 +00:00
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__ imulq(rdx, rcx, Immediate(12));
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__ imulq(rdx, rcx, Immediate(1000));
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2014-10-02 12:22:36 +00:00
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__ imulq(rdx, Operand(rbx, rcx, times_4, 10000));
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__ imulq(rdx, Operand(rbx, rcx, times_4, 10000), Immediate(12));
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2014-09-25 06:37:23 +00:00
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__ imulq(rdx, Operand(rbx, rcx, times_4, 10000), Immediate(1000));
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2014-10-02 12:22:36 +00:00
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__ imull(r15, rcx, Immediate(12));
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__ imull(r15, rcx, Immediate(1000));
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__ imull(r15, Operand(rbx, rcx, times_4, 10000));
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__ imull(r15, Operand(rbx, rcx, times_4, 10000), Immediate(12));
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__ imull(r15, Operand(rbx, rcx, times_4, 10000), Immediate(1000));
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2011-12-05 08:58:01 +00:00
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__ incq(rdx);
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__ incq(Operand(rbx, rcx, times_4, 10000));
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2014-03-19 08:59:04 +00:00
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__ pushq(Operand(rbx, rcx, times_4, 10000));
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__ popq(Operand(rbx, rcx, times_4, 10000));
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2019-01-28 13:01:36 +00:00
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__ jmp(Operand(rbx, rcx, times_4, 10000));
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2011-12-05 08:58:01 +00:00
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2014-03-26 11:17:53 +00:00
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__ leaq(rdx, Operand(rbx, rcx, times_4, 10000));
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2014-03-26 12:15:35 +00:00
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__ orq(rdx, Immediate(12345));
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__ orq(rdx, Operand(rbx, rcx, times_4, 10000));
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2011-12-05 08:58:01 +00:00
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__ nop();
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2014-03-28 04:55:00 +00:00
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__ rclq(rdx, Immediate(1));
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__ rclq(rdx, Immediate(7));
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__ rcrq(rdx, Immediate(1));
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__ rcrq(rdx, Immediate(7));
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__ sarq(rdx, Immediate(1));
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__ sarq(rdx, Immediate(6));
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__ sarq_cl(rdx);
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2011-12-05 08:58:01 +00:00
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__ sbbq(rdx, rbx);
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__ shld(rdx, rbx);
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2014-03-28 04:55:00 +00:00
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__ shlq(rdx, Immediate(1));
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__ shlq(rdx, Immediate(6));
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__ shlq_cl(rdx);
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2011-12-05 08:58:01 +00:00
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__ shrd(rdx, rbx);
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2014-03-28 04:55:00 +00:00
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__ shrq(rdx, Immediate(1));
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__ shrq(rdx, Immediate(7));
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__ shrq_cl(rdx);
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2011-12-05 08:58:01 +00:00
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// Immediates
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__ addq(rbx, Immediate(12));
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__ addq(Operand(rdx, rcx, times_4, 10000), Immediate(12));
|
|
|
|
|
|
2014-03-26 12:15:35 +00:00
|
|
|
__ andq(rbx, Immediate(12345));
|
2011-12-05 08:58:01 +00:00
|
|
|
|
|
|
|
|
__ cmpq(rbx, Immediate(12345));
|
|
|
|
|
__ cmpq(rbx, Immediate(12));
|
|
|
|
|
__ cmpq(Operand(rdx, rcx, times_4, 10000), Immediate(12));
|
|
|
|
|
__ cmpb(rax, Immediate(100));
|
|
|
|
|
|
2014-03-26 12:15:35 +00:00
|
|
|
__ orq(rbx, Immediate(12345));
|
2011-12-05 08:58:01 +00:00
|
|
|
|
|
|
|
|
__ subq(rbx, Immediate(12));
|
|
|
|
|
__ subq(Operand(rdx, rcx, times_4, 10000), Immediate(12));
|
|
|
|
|
|
2014-03-26 12:15:35 +00:00
|
|
|
__ xorq(rbx, Immediate(12345));
|
2011-12-05 08:58:01 +00:00
|
|
|
|
2014-03-21 02:42:10 +00:00
|
|
|
__ imulq(rdx, rcx, Immediate(12));
|
|
|
|
|
__ imulq(rdx, rcx, Immediate(1000));
|
2011-12-05 08:58:01 +00:00
|
|
|
|
|
|
|
|
__ cld();
|
|
|
|
|
|
|
|
|
|
__ subq(rdx, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ subq(rdx, rbx);
|
|
|
|
|
|
|
|
|
|
__ testq(rdx, Immediate(12345));
|
|
|
|
|
__ testq(Operand(rbx, rcx, times_8, 10000), rdx);
|
|
|
|
|
__ testb(Operand(rcx, rbx, times_2, 1000), rdx);
|
|
|
|
|
__ testb(Operand(rax, -20), Immediate(0x9A));
|
|
|
|
|
__ nop();
|
|
|
|
|
|
2014-03-26 12:15:35 +00:00
|
|
|
__ xorq(rdx, Immediate(12345));
|
|
|
|
|
__ xorq(rdx, Operand(rbx, rcx, times_8, 10000));
|
2011-12-05 08:58:01 +00:00
|
|
|
__ hlt();
|
|
|
|
|
__ int3();
|
|
|
|
|
__ ret(0);
|
|
|
|
|
__ ret(8);
|
|
|
|
|
|
|
|
|
|
// Calls
|
|
|
|
|
|
|
|
|
|
Label L1, L2;
|
|
|
|
|
__ bind(&L1);
|
|
|
|
|
__ nop();
|
|
|
|
|
__ call(&L1);
|
|
|
|
|
__ call(&L2);
|
|
|
|
|
__ nop();
|
|
|
|
|
__ bind(&L2);
|
2019-11-06 13:39:55 +00:00
|
|
|
__ call(rcx);
|
2011-12-05 08:58:01 +00:00
|
|
|
__ nop();
|
2019-11-04 10:01:19 +00:00
|
|
|
Handle<Code> ic = BUILTIN_CODE(isolate, ArrayFrom);
|
2011-12-05 08:58:01 +00:00
|
|
|
__ call(ic, RelocInfo::CODE_TARGET);
|
|
|
|
|
__ nop();
|
|
|
|
|
|
|
|
|
|
__ jmp(&L1);
|
2019-01-28 13:01:36 +00:00
|
|
|
__ jmp(Operand(rbx, rcx, times_4, 10000));
|
2011-12-05 08:58:01 +00:00
|
|
|
__ jmp(ic, RelocInfo::CODE_TARGET);
|
|
|
|
|
__ nop();
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Label Ljcc;
|
|
|
|
|
__ nop();
|
|
|
|
|
// long jumps
|
|
|
|
|
__ j(overflow, &Ljcc);
|
|
|
|
|
__ j(no_overflow, &Ljcc);
|
|
|
|
|
__ j(below, &Ljcc);
|
|
|
|
|
__ j(above_equal, &Ljcc);
|
|
|
|
|
__ j(equal, &Ljcc);
|
|
|
|
|
__ j(not_equal, &Ljcc);
|
|
|
|
|
__ j(below_equal, &Ljcc);
|
|
|
|
|
__ j(above, &Ljcc);
|
|
|
|
|
__ j(sign, &Ljcc);
|
|
|
|
|
__ j(not_sign, &Ljcc);
|
|
|
|
|
__ j(parity_even, &Ljcc);
|
|
|
|
|
__ j(parity_odd, &Ljcc);
|
|
|
|
|
__ j(less, &Ljcc);
|
|
|
|
|
__ j(greater_equal, &Ljcc);
|
|
|
|
|
__ j(less_equal, &Ljcc);
|
|
|
|
|
__ j(greater, &Ljcc);
|
|
|
|
|
__ nop();
|
|
|
|
|
__ bind(&Ljcc);
|
|
|
|
|
// short jumps
|
|
|
|
|
__ j(overflow, &Ljcc);
|
|
|
|
|
__ j(no_overflow, &Ljcc);
|
|
|
|
|
__ j(below, &Ljcc);
|
|
|
|
|
__ j(above_equal, &Ljcc);
|
|
|
|
|
__ j(equal, &Ljcc);
|
|
|
|
|
__ j(not_equal, &Ljcc);
|
|
|
|
|
__ j(below_equal, &Ljcc);
|
|
|
|
|
__ j(above, &Ljcc);
|
|
|
|
|
__ j(sign, &Ljcc);
|
|
|
|
|
__ j(not_sign, &Ljcc);
|
|
|
|
|
__ j(parity_even, &Ljcc);
|
|
|
|
|
__ j(parity_odd, &Ljcc);
|
|
|
|
|
__ j(less, &Ljcc);
|
|
|
|
|
__ j(greater_equal, &Ljcc);
|
|
|
|
|
__ j(less_equal, &Ljcc);
|
|
|
|
|
__ j(greater, &Ljcc);
|
|
|
|
|
|
|
|
|
|
// 0xD9 instructions
|
|
|
|
|
__ nop();
|
|
|
|
|
|
|
|
|
|
__ fld(1);
|
|
|
|
|
__ fld1();
|
|
|
|
|
__ fldz();
|
|
|
|
|
__ fldpi();
|
|
|
|
|
__ fabs();
|
|
|
|
|
__ fchs();
|
|
|
|
|
__ fprem();
|
|
|
|
|
__ fprem1();
|
|
|
|
|
__ fincstp();
|
|
|
|
|
__ ftst();
|
|
|
|
|
__ fxch(3);
|
|
|
|
|
__ fld_s(Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ fstp_s(Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ ffree(3);
|
|
|
|
|
__ fld_d(Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ fstp_d(Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ nop();
|
|
|
|
|
|
|
|
|
|
__ fild_s(Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ fistp_s(Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ fild_d(Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ fistp_d(Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ fnstsw_ax();
|
|
|
|
|
__ nop();
|
|
|
|
|
__ fadd(3);
|
|
|
|
|
__ fsub(3);
|
|
|
|
|
__ fmul(3);
|
|
|
|
|
__ fdiv(3);
|
|
|
|
|
|
|
|
|
|
__ faddp(3);
|
|
|
|
|
__ fsubp(3);
|
|
|
|
|
__ fmulp(3);
|
|
|
|
|
__ fdivp(3);
|
|
|
|
|
__ fcompp();
|
|
|
|
|
__ fwait();
|
2014-02-03 08:13:12 +00:00
|
|
|
__ frndint();
|
|
|
|
|
__ fninit();
|
2011-12-05 08:58:01 +00:00
|
|
|
__ nop();
|
2013-10-28 10:38:40 +00:00
|
|
|
|
|
|
|
|
// SSE instruction
|
2011-12-05 08:58:01 +00:00
|
|
|
{
|
2013-11-18 15:24:41 +00:00
|
|
|
// Move operation
|
2013-10-28 10:38:40 +00:00
|
|
|
__ cvttss2si(rdx, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ cvttss2si(rdx, xmm1);
|
2020-04-06 16:44:23 +00:00
|
|
|
__ cvtqsi2ss(xmm1, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ cvtqsi2ss(xmm1, rdx);
|
2018-08-14 19:38:14 +00:00
|
|
|
__ cvttps2dq(xmm0, xmm1);
|
|
|
|
|
__ cvttps2dq(xmm0, Operand(rbx, rcx, times_4, 10000));
|
2013-10-28 10:38:40 +00:00
|
|
|
__ movaps(xmm0, xmm1);
|
2017-12-18 14:32:23 +00:00
|
|
|
__ movdqa(xmm0, Operand(rsp, 12));
|
|
|
|
|
__ movdqa(Operand(rsp, 12), xmm0);
|
|
|
|
|
__ movdqu(xmm0, Operand(rsp, 12));
|
|
|
|
|
__ movdqu(Operand(rsp, 12), xmm0);
|
2017-01-26 01:38:17 +00:00
|
|
|
__ shufps(xmm0, xmm9, 0x0);
|
2011-12-05 08:58:01 +00:00
|
|
|
|
2014-11-26 05:31:41 +00:00
|
|
|
__ ucomiss(xmm0, xmm1);
|
|
|
|
|
__ ucomiss(xmm0, Operand(rbx, rcx, times_4, 10000));
|
2019-10-21 22:04:20 +00:00
|
|
|
|
2020-04-06 16:44:23 +00:00
|
|
|
__ movmskps(rdx, xmm9);
|
|
|
|
|
|
2019-10-21 22:04:20 +00:00
|
|
|
#define EMIT_SSE_INSTR(instruction, notUsed1, notUsed2) \
|
|
|
|
|
__ instruction(xmm1, xmm0); \
|
|
|
|
|
__ instruction(xmm1, Operand(rbx, rcx, times_4, 10000));
|
2019-11-25 19:26:01 +00:00
|
|
|
SSE_BINOP_INSTRUCTION_LIST(EMIT_SSE_INSTR)
|
|
|
|
|
SSE_UNOP_INSTRUCTION_LIST(EMIT_SSE_INSTR)
|
2019-10-21 22:04:20 +00:00
|
|
|
#undef EMIT_SSE_INSTR
|
2019-10-29 18:27:55 +00:00
|
|
|
|
|
|
|
|
#define EMIT_SSE_INSTR(instruction, notUsed1, notUsed2, notUse3) \
|
|
|
|
|
__ instruction(xmm1, xmm0); \
|
|
|
|
|
__ instruction(xmm1, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
SSE_INSTRUCTION_LIST_SS(EMIT_SSE_INSTR)
|
|
|
|
|
#undef EMIT_SSE_INSTR
|
2013-10-28 10:38:40 +00:00
|
|
|
}
|
2016-09-12 06:24:06 +00:00
|
|
|
|
|
|
|
|
// SSE2 instructions
|
2011-12-05 08:58:01 +00:00
|
|
|
{
|
2013-10-28 10:38:40 +00:00
|
|
|
__ cvttsd2si(rdx, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ cvttsd2si(rdx, xmm1);
|
|
|
|
|
__ cvttsd2siq(rdx, xmm1);
|
2014-09-19 14:25:13 +00:00
|
|
|
__ cvttsd2siq(rdx, Operand(rbx, rcx, times_4, 10000));
|
2020-04-06 16:44:23 +00:00
|
|
|
__ cvtlsi2sd(xmm1, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ cvtlsi2sd(xmm1, rdx);
|
2014-09-30 10:24:11 +00:00
|
|
|
__ cvtqsi2sd(xmm1, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ cvtqsi2sd(xmm1, rdx);
|
2020-04-06 16:44:23 +00:00
|
|
|
__ cvtss2sd(xmm1, xmm9);
|
|
|
|
|
__ cvtss2sd(xmm1, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ cvtsd2si(rdx, xmm9);
|
|
|
|
|
__ cvtsd2siq(rdx, xmm9);
|
|
|
|
|
|
2013-10-28 10:38:40 +00:00
|
|
|
__ movsd(xmm1, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ movsd(Operand(rbx, rcx, times_4, 10000), xmm1);
|
|
|
|
|
// 128 bit move instructions.
|
2016-07-21 11:01:44 +00:00
|
|
|
__ movupd(xmm0, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ movupd(Operand(rbx, rcx, times_4, 10000), xmm0);
|
2013-10-28 10:38:40 +00:00
|
|
|
__ movdqa(xmm0, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ movdqa(Operand(rbx, rcx, times_4, 10000), xmm0);
|
|
|
|
|
|
|
|
|
|
__ ucomisd(xmm0, xmm1);
|
2020-04-06 16:44:23 +00:00
|
|
|
__ ucomisd(xmm8, Operand(rbx, rdx, times_4, 10000));
|
2013-10-28 10:38:40 +00:00
|
|
|
|
2020-04-06 16:44:23 +00:00
|
|
|
__ cmpltsd(xmm3, xmm11);
|
|
|
|
|
|
|
|
|
|
__ movmskpd(rdx, xmm9);
|
2020-04-06 16:42:49 +00:00
|
|
|
__ pmovmskb(rdx, xmm9);
|
|
|
|
|
|
2014-10-17 04:18:38 +00:00
|
|
|
__ pcmpeqd(xmm1, xmm0);
|
2015-03-05 09:22:26 +00:00
|
|
|
|
|
|
|
|
__ punpckldq(xmm1, xmm11);
|
2016-06-17 09:26:58 +00:00
|
|
|
__ punpckldq(xmm5, Operand(rdx, 4));
|
2015-03-05 09:22:26 +00:00
|
|
|
__ punpckhdq(xmm8, xmm15);
|
2016-09-12 06:24:06 +00:00
|
|
|
|
[wasm] Implement wasm x64 I16x8 Ops
- Add I16x8 Splat, ExtractLane, ReplaceLane, shift ops, Some BinOps and compare ops
- Add pshufhw, pshuflw in the assembler, disassembler
- Fix incorrect modrm for pextrw, this bug disregards the register allocated and always makes pextrw use rax.
- Fix pextrw disasm to take the 0 - 7 bits of the immediate instead of 0 - 3.
- Pextrw, pinsrw are in the assembler use 128 bit encodings, pextrw, pinsrw in the disassembler use legacy encodings, fix inconsistencies causing weird code gen when --print-code is used.
Review-Url: https://codereview.chromium.org/2767983002
Cr-Commit-Position: refs/heads/master@{#44664}
2017-04-17 18:47:46 +00:00
|
|
|
__ pshuflw(xmm2, xmm4, 3);
|
|
|
|
|
__ pshufhw(xmm1, xmm9, 6);
|
|
|
|
|
|
2016-09-12 06:24:06 +00:00
|
|
|
#define EMIT_SSE2_INSTR(instruction, notUsed1, notUsed2, notUsed3) \
|
|
|
|
|
__ instruction(xmm5, xmm1); \
|
|
|
|
|
__ instruction(xmm5, Operand(rdx, 4));
|
|
|
|
|
|
|
|
|
|
SSE2_INSTRUCTION_LIST(EMIT_SSE2_INSTR)
|
Fix assembler for sqrtpd
The assembly of sqrtpd when using Sqrtpd macro was wrong, since
Sqrtpd(xmm1, xmm1) will incorrect generated vsqrtpd(xmm1, xmm1, xmm1),
which is nonsensical, since vsqrtpd only takes two operands. The
expected instruction should be vsqrtpd(xmm1, xmm0, xmm1) in terms of the
encoding, which is vsqrtpd(xmm1, xmm1).
So, move sqrtpd and cvtps2dq out into their own macro list, because
they have two operands in their AVX form, unlike the rest of the
instructions in SSE2_INSTRUCTION_LIST.
Also updated disasm and tests to use this new list.
Fixed: v8:10170
Change-Id: Ia9343c9a3ae64596bbc876744556e1dcea2a443b
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2032195
Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#66088}
2020-01-31 18:28:11 +00:00
|
|
|
SSE2_UNOP_INSTRUCTION_LIST(EMIT_SSE2_INSTR)
|
2019-10-30 19:45:10 +00:00
|
|
|
SSE2_INSTRUCTION_LIST_SD(EMIT_SSE2_INSTR)
|
2016-09-12 06:24:06 +00:00
|
|
|
#undef EMIT_SSE2_INSTR
|
2019-12-04 14:56:48 +00:00
|
|
|
|
|
|
|
|
#define EMIT_SSE2_SHIFT_IMM(instruction, notUsed1, notUsed2, notUsed3, \
|
|
|
|
|
notUsed4) \
|
|
|
|
|
__ instruction(xmm3, 0xA3);
|
|
|
|
|
SSE2_INSTRUCTION_LIST_SHIFT_IMM(EMIT_SSE2_SHIFT_IMM)
|
|
|
|
|
#undef EMIT_SSE2_SHIFT_IMM
|
2011-12-05 08:58:01 +00:00
|
|
|
}
|
|
|
|
|
|
2013-10-28 10:38:40 +00:00
|
|
|
// cmov.
|
2011-12-05 08:58:01 +00:00
|
|
|
{
|
2013-10-28 10:38:40 +00:00
|
|
|
__ cmovq(overflow, rax, Operand(rax, 0));
|
|
|
|
|
__ cmovq(no_overflow, rax, Operand(rax, 1));
|
|
|
|
|
__ cmovq(below, rax, Operand(rax, 2));
|
|
|
|
|
__ cmovq(above_equal, rax, Operand(rax, 3));
|
|
|
|
|
__ cmovq(equal, rax, Operand(rbx, 0));
|
|
|
|
|
__ cmovq(not_equal, rax, Operand(rbx, 1));
|
|
|
|
|
__ cmovq(below_equal, rax, Operand(rbx, 2));
|
|
|
|
|
__ cmovq(above, rax, Operand(rbx, 3));
|
|
|
|
|
__ cmovq(sign, rax, Operand(rcx, 0));
|
|
|
|
|
__ cmovq(not_sign, rax, Operand(rcx, 1));
|
|
|
|
|
__ cmovq(parity_even, rax, Operand(rcx, 2));
|
|
|
|
|
__ cmovq(parity_odd, rax, Operand(rcx, 3));
|
|
|
|
|
__ cmovq(less, rax, Operand(rdx, 0));
|
|
|
|
|
__ cmovq(greater_equal, rax, Operand(rdx, 1));
|
|
|
|
|
__ cmovq(less_equal, rax, Operand(rdx, 2));
|
|
|
|
|
__ cmovq(greater, rax, Operand(rdx, 3));
|
2011-12-05 08:58:01 +00:00
|
|
|
}
|
|
|
|
|
|
2016-09-12 06:24:06 +00:00
|
|
|
{
|
|
|
|
|
if (CpuFeatures::IsSupported(SSE3)) {
|
|
|
|
|
CpuFeatureScope scope(&assm, SSE3);
|
2018-02-28 06:28:08 +00:00
|
|
|
__ haddps(xmm1, xmm0);
|
|
|
|
|
__ haddps(xmm1, Operand(rbx, rcx, times_4, 10000));
|
2016-09-12 06:24:06 +00:00
|
|
|
__ lddqu(xmm1, Operand(rdx, 4));
|
2019-07-26 00:00:22 +00:00
|
|
|
__ movddup(xmm1, Operand(rax, 5));
|
|
|
|
|
__ movddup(xmm1, xmm2);
|
2016-09-12 06:24:06 +00:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#define EMIT_SSE34_INSTR(instruction, notUsed1, notUsed2, notUsed3, notUsed4) \
|
|
|
|
|
__ instruction(xmm5, xmm1); \
|
|
|
|
|
__ instruction(xmm5, Operand(rdx, 4));
|
|
|
|
|
|
2019-10-30 04:38:36 +00:00
|
|
|
#define EMIT_SSE34_IMM_INSTR(instruction, notUsed1, notUsed2, notUsed3, \
|
|
|
|
|
notUsed4) \
|
|
|
|
|
__ instruction(rbx, xmm15, 0); \
|
|
|
|
|
__ instruction(Operand(rax, 10), xmm0, 1);
|
|
|
|
|
|
2016-09-12 06:24:06 +00:00
|
|
|
{
|
|
|
|
|
if (CpuFeatures::IsSupported(SSSE3)) {
|
|
|
|
|
CpuFeatureScope scope(&assm, SSSE3);
|
2018-08-14 19:38:14 +00:00
|
|
|
__ palignr(xmm5, xmm1, 5);
|
|
|
|
|
__ palignr(xmm5, Operand(rdx, 4), 5);
|
2016-09-12 06:24:06 +00:00
|
|
|
SSSE3_INSTRUCTION_LIST(EMIT_SSE34_INSTR)
|
2020-02-19 10:26:51 +00:00
|
|
|
SSSE3_UNOP_INSTRUCTION_LIST(EMIT_SSE34_INSTR)
|
2016-09-12 06:24:06 +00:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2013-10-15 12:51:58 +00:00
|
|
|
{
|
|
|
|
|
if (CpuFeatures::IsSupported(SSE4_1)) {
|
|
|
|
|
CpuFeatureScope scope(&assm, SSE4_1);
|
2016-05-19 19:52:59 +00:00
|
|
|
__ insertps(xmm5, xmm1, 123);
|
[wasm] Implement wasm x64 I16x8 Ops
- Add I16x8 Splat, ExtractLane, ReplaceLane, shift ops, Some BinOps and compare ops
- Add pshufhw, pshuflw in the assembler, disassembler
- Fix incorrect modrm for pextrw, this bug disregards the register allocated and always makes pextrw use rax.
- Fix pextrw disasm to take the 0 - 7 bits of the immediate instead of 0 - 3.
- Pextrw, pinsrw are in the assembler use 128 bit encodings, pextrw, pinsrw in the disassembler use legacy encodings, fix inconsistencies causing weird code gen when --print-code is used.
Review-Url: https://codereview.chromium.org/2767983002
Cr-Commit-Position: refs/heads/master@{#44664}
2017-04-17 18:47:46 +00:00
|
|
|
__ pinsrw(xmm2, rcx, 1);
|
2019-07-01 23:58:02 +00:00
|
|
|
__ pextrq(r12, xmm0, 1);
|
2015-03-05 09:22:26 +00:00
|
|
|
__ pinsrd(xmm9, r9, 0);
|
2016-05-19 19:52:59 +00:00
|
|
|
__ pinsrd(xmm5, Operand(rax, 4), 1);
|
2019-07-01 23:58:02 +00:00
|
|
|
__ pinsrq(xmm9, r9, 0);
|
|
|
|
|
__ pinsrq(xmm5, Operand(rax, 4), 1);
|
2018-08-14 19:38:14 +00:00
|
|
|
__ pblendw(xmm5, xmm1, 1);
|
|
|
|
|
__ pblendw(xmm9, Operand(rax, 4), 1);
|
2016-05-19 19:52:59 +00:00
|
|
|
|
|
|
|
|
__ cmpps(xmm5, xmm1, 1);
|
2016-08-03 15:23:57 +00:00
|
|
|
__ cmpps(xmm5, Operand(rbx, rcx, times_4, 10000), 1);
|
2016-05-19 19:52:59 +00:00
|
|
|
__ cmpeqps(xmm5, xmm1);
|
2016-08-03 15:23:57 +00:00
|
|
|
__ cmpeqps(xmm5, Operand(rbx, rcx, times_4, 10000));
|
2016-05-19 19:52:59 +00:00
|
|
|
__ cmpltps(xmm5, xmm1);
|
2016-08-03 15:23:57 +00:00
|
|
|
__ cmpltps(xmm5, Operand(rbx, rcx, times_4, 10000));
|
2016-05-19 19:52:59 +00:00
|
|
|
__ cmpleps(xmm5, xmm1);
|
2016-08-03 15:23:57 +00:00
|
|
|
__ cmpleps(xmm5, Operand(rbx, rcx, times_4, 10000));
|
2016-05-19 19:52:59 +00:00
|
|
|
__ cmpneqps(xmm5, xmm1);
|
2016-08-03 15:23:57 +00:00
|
|
|
__ cmpneqps(xmm5, Operand(rbx, rcx, times_4, 10000));
|
2016-05-19 19:52:59 +00:00
|
|
|
__ cmpnltps(xmm5, xmm1);
|
2016-08-03 15:23:57 +00:00
|
|
|
__ cmpnltps(xmm5, Operand(rbx, rcx, times_4, 10000));
|
2016-05-19 19:52:59 +00:00
|
|
|
__ cmpnleps(xmm5, xmm1);
|
2016-08-03 15:23:57 +00:00
|
|
|
__ cmpnleps(xmm5, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ cmppd(xmm5, xmm1, 1);
|
|
|
|
|
__ cmppd(xmm5, Operand(rbx, rcx, times_4, 10000), 1);
|
|
|
|
|
__ cmpeqpd(xmm5, xmm1);
|
|
|
|
|
__ cmpeqpd(xmm5, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ cmpltpd(xmm5, xmm1);
|
|
|
|
|
__ cmpltpd(xmm5, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ cmplepd(xmm5, xmm1);
|
|
|
|
|
__ cmplepd(xmm5, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ cmpneqpd(xmm5, xmm1);
|
|
|
|
|
__ cmpneqpd(xmm5, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ cmpnltpd(xmm5, xmm1);
|
|
|
|
|
__ cmpnltpd(xmm5, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ cmpnlepd(xmm5, xmm1);
|
|
|
|
|
__ cmpnlepd(xmm5, Operand(rbx, rcx, times_4, 10000));
|
2016-05-19 19:52:59 +00:00
|
|
|
|
|
|
|
|
__ movups(xmm5, xmm1);
|
|
|
|
|
__ movups(xmm5, Operand(rdx, 4));
|
|
|
|
|
__ movups(Operand(rdx, 4), xmm5);
|
2019-10-16 20:21:00 +00:00
|
|
|
__ movlhps(xmm5, xmm1);
|
2016-05-19 19:52:59 +00:00
|
|
|
__ pmulld(xmm5, xmm1);
|
|
|
|
|
__ pmulld(xmm5, Operand(rdx, 4));
|
2016-09-12 06:24:06 +00:00
|
|
|
__ pmullw(xmm5, xmm1);
|
|
|
|
|
__ pmullw(xmm5, Operand(rdx, 4));
|
2016-05-19 19:52:59 +00:00
|
|
|
__ pmuludq(xmm5, xmm1);
|
|
|
|
|
__ pmuludq(xmm5, Operand(rdx, 4));
|
|
|
|
|
__ psrldq(xmm5, 123);
|
|
|
|
|
__ pshufd(xmm5, xmm1, 3);
|
|
|
|
|
__ cvtps2dq(xmm5, xmm1);
|
|
|
|
|
__ cvtps2dq(xmm5, Operand(rdx, 4));
|
|
|
|
|
__ cvtdq2ps(xmm5, xmm1);
|
|
|
|
|
__ cvtdq2ps(xmm5, Operand(rdx, 4));
|
2020-01-10 17:54:44 +00:00
|
|
|
__ blendvpd(xmm5, xmm1);
|
|
|
|
|
__ blendvpd(xmm5, Operand(rdx, 4));
|
2016-09-12 06:24:06 +00:00
|
|
|
|
2020-04-06 16:44:23 +00:00
|
|
|
__ roundss(xmm8, xmm3, kRoundDown);
|
|
|
|
|
__ roundsd(xmm8, xmm3, kRoundDown);
|
|
|
|
|
|
2016-09-12 06:24:06 +00:00
|
|
|
SSE4_INSTRUCTION_LIST(EMIT_SSE34_INSTR)
|
2020-02-27 08:45:39 +00:00
|
|
|
SSE4_UNOP_INSTRUCTION_LIST(EMIT_SSE34_INSTR)
|
2019-10-30 04:38:36 +00:00
|
|
|
SSE4_EXTRACT_INSTRUCTION_LIST(EMIT_SSE34_IMM_INSTR)
|
2013-10-15 12:51:58 +00:00
|
|
|
}
|
|
|
|
|
}
|
2019-07-16 08:50:27 +00:00
|
|
|
|
|
|
|
|
{
|
|
|
|
|
if (CpuFeatures::IsSupported(SSE4_2)) {
|
|
|
|
|
CpuFeatureScope scope(&assm, SSE4_2);
|
|
|
|
|
|
|
|
|
|
SSE4_2_INSTRUCTION_LIST(EMIT_SSE34_INSTR)
|
|
|
|
|
}
|
|
|
|
|
}
|
2016-09-12 06:24:06 +00:00
|
|
|
#undef EMIT_SSE34_INSTR
|
2019-10-30 04:38:36 +00:00
|
|
|
#undef EMIT_SSE34_IMM_INSTR
|
2013-10-15 12:51:58 +00:00
|
|
|
|
2014-12-01 10:45:02 +00:00
|
|
|
// AVX instruction
|
|
|
|
|
{
|
|
|
|
|
if (CpuFeatures::IsSupported(AVX)) {
|
|
|
|
|
CpuFeatureScope scope(&assm, AVX);
|
2015-10-20 04:58:07 +00:00
|
|
|
__ vmovss(xmm6, xmm14, xmm2);
|
|
|
|
|
__ vmovss(xmm9, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ vmovss(Operand(rbx, rcx, times_4, 10000), xmm0);
|
|
|
|
|
|
2015-03-30 07:33:46 +00:00
|
|
|
__ vaddss(xmm0, xmm1, xmm2);
|
|
|
|
|
__ vaddss(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ vmulss(xmm0, xmm1, xmm2);
|
|
|
|
|
__ vmulss(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ vsubss(xmm0, xmm1, xmm2);
|
|
|
|
|
__ vsubss(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ vdivss(xmm0, xmm1, xmm2);
|
|
|
|
|
__ vdivss(xmm0, xmm1, Operand(rbx, rcx, times_2, 10000));
|
|
|
|
|
__ vminss(xmm8, xmm1, xmm2);
|
|
|
|
|
__ vminss(xmm9, xmm1, Operand(rbx, rcx, times_8, 10000));
|
|
|
|
|
__ vmaxss(xmm8, xmm1, xmm2);
|
|
|
|
|
__ vmaxss(xmm9, xmm1, Operand(rbx, rcx, times_1, 10000));
|
2018-03-03 08:53:21 +00:00
|
|
|
__ vsqrtss(xmm8, xmm1, xmm2);
|
|
|
|
|
__ vsqrtss(xmm9, xmm1, Operand(rbx, rcx, times_1, 10000));
|
2015-10-19 20:35:17 +00:00
|
|
|
__ vmovss(xmm9, Operand(r11, rcx, times_8, -10000));
|
|
|
|
|
__ vmovss(Operand(rbx, r9, times_4, 10000), xmm1);
|
2015-03-30 07:33:46 +00:00
|
|
|
__ vucomiss(xmm9, xmm1);
|
|
|
|
|
__ vucomiss(xmm8, Operand(rbx, rdx, times_2, 10981));
|
|
|
|
|
|
2015-10-16 05:20:31 +00:00
|
|
|
__ vmovd(xmm5, rdi);
|
|
|
|
|
__ vmovd(xmm9, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ vmovd(r9, xmm6);
|
|
|
|
|
__ vmovq(xmm5, rdi);
|
|
|
|
|
__ vmovq(xmm9, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ vmovq(r9, xmm6);
|
|
|
|
|
|
2015-10-20 04:58:07 +00:00
|
|
|
__ vmovsd(xmm6, xmm14, xmm2);
|
2015-10-15 04:14:31 +00:00
|
|
|
__ vmovsd(xmm9, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ vmovsd(Operand(rbx, rcx, times_4, 10000), xmm0);
|
|
|
|
|
|
2019-10-18 23:58:10 +00:00
|
|
|
__ vmovdqu(xmm9, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ vmovdqu(Operand(rbx, rcx, times_4, 10000), xmm0);
|
|
|
|
|
|
2020-01-10 17:55:04 +00:00
|
|
|
__ vroundss(xmm9, xmm1, xmm2, kRoundDown);
|
2015-10-23 07:48:54 +00:00
|
|
|
__ vroundsd(xmm8, xmm3, xmm0, kRoundDown);
|
2015-03-30 07:33:46 +00:00
|
|
|
__ vucomisd(xmm9, xmm1);
|
|
|
|
|
__ vucomisd(xmm8, Operand(rbx, rdx, times_2, 10981));
|
2015-10-18 15:43:07 +00:00
|
|
|
|
2015-10-18 16:11:11 +00:00
|
|
|
__ vcvtss2sd(xmm4, xmm9, xmm11);
|
|
|
|
|
__ vcvtss2sd(xmm4, xmm9, Operand(rbx, rcx, times_1, 10000));
|
2020-03-03 04:46:45 +00:00
|
|
|
__ vcvttps2dq(xmm4, xmm11);
|
2015-10-15 17:50:03 +00:00
|
|
|
__ vcvtlsi2sd(xmm5, xmm9, rcx);
|
|
|
|
|
__ vcvtlsi2sd(xmm9, xmm3, Operand(rbx, r9, times_4, 10000));
|
2015-10-24 16:49:35 +00:00
|
|
|
__ vcvtqsi2sd(xmm5, xmm9, r11);
|
2015-10-18 15:43:07 +00:00
|
|
|
__ vcvttsd2si(r9, xmm6);
|
|
|
|
|
__ vcvttsd2si(rax, Operand(rbx, r9, times_4, 10000));
|
|
|
|
|
__ vcvttsd2siq(rdi, xmm9);
|
|
|
|
|
__ vcvttsd2siq(r8, Operand(r9, rbx, times_4, 10000));
|
2015-10-24 18:55:27 +00:00
|
|
|
__ vcvtsd2si(rdi, xmm9);
|
2015-04-11 01:02:22 +00:00
|
|
|
|
2015-10-20 04:58:07 +00:00
|
|
|
__ vmovaps(xmm10, xmm11);
|
2015-10-18 16:12:24 +00:00
|
|
|
__ vmovapd(xmm7, xmm0);
|
2016-07-21 11:01:44 +00:00
|
|
|
__ vmovupd(xmm0, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ vmovupd(Operand(rbx, rcx, times_4, 10000), xmm0);
|
2015-10-18 16:12:24 +00:00
|
|
|
__ vmovmskpd(r9, xmm4);
|
2020-04-06 16:42:49 +00:00
|
|
|
__ vpmovmskb(r10, xmm9);
|
2015-10-18 16:12:24 +00:00
|
|
|
|
2016-07-11 18:18:17 +00:00
|
|
|
__ vmovups(xmm5, xmm1);
|
|
|
|
|
__ vmovups(xmm5, Operand(rdx, 4));
|
|
|
|
|
__ vmovups(Operand(rdx, 4), xmm5);
|
2020-01-08 19:45:32 +00:00
|
|
|
__ vmovlhps(xmm1, xmm3, xmm5);
|
2016-07-11 18:18:17 +00:00
|
|
|
|
2015-04-11 01:02:22 +00:00
|
|
|
__ vandps(xmm0, xmm9, xmm2);
|
|
|
|
|
__ vandps(xmm9, xmm1, Operand(rbx, rcx, times_4, 10000));
|
2019-03-21 20:30:49 +00:00
|
|
|
__ vandnps(xmm0, xmm9, xmm2);
|
|
|
|
|
__ vandnps(xmm9, xmm1, Operand(rbx, rcx, times_4, 10000));
|
2015-04-11 01:02:22 +00:00
|
|
|
__ vxorps(xmm0, xmm1, xmm9);
|
|
|
|
|
__ vxorps(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
|
2018-02-28 06:28:08 +00:00
|
|
|
__ vhaddps(xmm0, xmm1, xmm9);
|
|
|
|
|
__ vhaddps(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
|
2015-04-11 01:02:22 +00:00
|
|
|
|
2015-10-22 07:00:57 +00:00
|
|
|
__ vpcmpeqd(xmm0, xmm15, xmm5);
|
|
|
|
|
__ vpcmpeqd(xmm15, xmm0, Operand(rbx, rcx, times_4, 10000));
|
2016-08-03 15:23:57 +00:00
|
|
|
|
|
|
|
|
__ vcmpps(xmm5, xmm4, xmm1, 1);
|
|
|
|
|
__ vcmpps(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000), 1);
|
|
|
|
|
__ vcmpeqps(xmm5, xmm4, xmm1);
|
|
|
|
|
__ vcmpeqps(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ vcmpltps(xmm5, xmm4, xmm1);
|
|
|
|
|
__ vcmpltps(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ vcmpleps(xmm5, xmm4, xmm1);
|
|
|
|
|
__ vcmpleps(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ vcmpneqps(xmm5, xmm4, xmm1);
|
|
|
|
|
__ vcmpneqps(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ vcmpnltps(xmm5, xmm4, xmm1);
|
|
|
|
|
__ vcmpnltps(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ vcmpnleps(xmm5, xmm4, xmm1);
|
|
|
|
|
__ vcmpnleps(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ vcmppd(xmm5, xmm4, xmm1, 1);
|
|
|
|
|
__ vcmppd(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000), 1);
|
|
|
|
|
__ vcmpeqpd(xmm5, xmm4, xmm1);
|
|
|
|
|
__ vcmpeqpd(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ vcmpltpd(xmm5, xmm4, xmm1);
|
|
|
|
|
__ vcmpltpd(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ vcmplepd(xmm5, xmm4, xmm1);
|
|
|
|
|
__ vcmplepd(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ vcmpneqpd(xmm5, xmm4, xmm1);
|
|
|
|
|
__ vcmpneqpd(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ vcmpnltpd(xmm5, xmm4, xmm1);
|
|
|
|
|
__ vcmpnltpd(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ vcmpnlepd(xmm5, xmm4, xmm1);
|
|
|
|
|
__ vcmpnlepd(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
|
2016-09-12 06:24:06 +00:00
|
|
|
|
2019-11-25 19:26:01 +00:00
|
|
|
#define EMIT_SSE_UNOP_AVXINSTR(instruction, notUsed1, notUsed2) \
|
|
|
|
|
__ v##instruction(xmm10, xmm1); \
|
|
|
|
|
__ v##instruction(xmm10, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
|
|
|
|
|
SSE_UNOP_INSTRUCTION_LIST(EMIT_SSE_UNOP_AVXINSTR)
|
|
|
|
|
#undef EMIT_SSE_UNOP_AVXINSTR
|
|
|
|
|
|
|
|
|
|
#define EMIT_SSE_BINOP_AVXINSTR(instruction, notUsed1, notUsed2) \
|
|
|
|
|
__ v##instruction(xmm10, xmm5, xmm1); \
|
|
|
|
|
__ v##instruction(xmm10, xmm5, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
|
|
|
|
|
SSE_BINOP_INSTRUCTION_LIST(EMIT_SSE_BINOP_AVXINSTR)
|
|
|
|
|
#undef EMIT_SSE_BINOP_AVXINSTR
|
|
|
|
|
|
2016-09-12 06:24:06 +00:00
|
|
|
#define EMIT_SSE2_AVXINSTR(instruction, notUsed1, notUsed2, notUsed3) \
|
|
|
|
|
__ v##instruction(xmm10, xmm5, xmm1); \
|
|
|
|
|
__ v##instruction(xmm10, xmm5, Operand(rdx, 4));
|
|
|
|
|
|
Fix assembler for sqrtpd
The assembly of sqrtpd when using Sqrtpd macro was wrong, since
Sqrtpd(xmm1, xmm1) will incorrect generated vsqrtpd(xmm1, xmm1, xmm1),
which is nonsensical, since vsqrtpd only takes two operands. The
expected instruction should be vsqrtpd(xmm1, xmm0, xmm1) in terms of the
encoding, which is vsqrtpd(xmm1, xmm1).
So, move sqrtpd and cvtps2dq out into their own macro list, because
they have two operands in their AVX form, unlike the rest of the
instructions in SSE2_INSTRUCTION_LIST.
Also updated disasm and tests to use this new list.
Fixed: v8:10170
Change-Id: Ia9343c9a3ae64596bbc876744556e1dcea2a443b
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2032195
Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#66088}
2020-01-31 18:28:11 +00:00
|
|
|
SSE2_INSTRUCTION_LIST(EMIT_SSE2_AVXINSTR)
|
|
|
|
|
#undef EMIT_SSE2_AVXINSTR
|
|
|
|
|
|
|
|
|
|
#define EMIT_SSE2_UNOP_AVXINSTR(instruction, notUsed1, notUsed2, notUsed3) \
|
|
|
|
|
__ v##instruction(xmm10, xmm1); \
|
|
|
|
|
__ v##instruction(xmm10, Operand(rdx, 4));
|
|
|
|
|
|
|
|
|
|
SSE2_UNOP_INSTRUCTION_LIST(EMIT_SSE2_UNOP_AVXINSTR)
|
|
|
|
|
#undef EMIT_SSE2_AVXINSTR
|
|
|
|
|
|
2020-02-03 22:51:57 +00:00
|
|
|
#define EMIT_SSE2_SD_AVXINSTR(instruction, notUsed1, notUsed2, notUsed3) \
|
|
|
|
|
__ v##instruction(xmm10, xmm5, xmm1); \
|
|
|
|
|
__ v##instruction(xmm10, xmm5, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
SSE2_INSTRUCTION_LIST_SD(EMIT_SSE2_SD_AVXINSTR)
|
|
|
|
|
#undef EMIT_SSE2_SD_AVXINSTR
|
|
|
|
|
|
2016-09-12 06:24:06 +00:00
|
|
|
#define EMIT_SSE34_AVXINSTR(instruction, notUsed1, notUsed2, notUsed3, \
|
|
|
|
|
notUsed4) \
|
|
|
|
|
__ v##instruction(xmm10, xmm5, xmm1); \
|
|
|
|
|
__ v##instruction(xmm10, xmm5, Operand(rdx, 4));
|
|
|
|
|
|
|
|
|
|
SSSE3_INSTRUCTION_LIST(EMIT_SSE34_AVXINSTR)
|
|
|
|
|
SSE4_INSTRUCTION_LIST(EMIT_SSE34_AVXINSTR)
|
2020-01-10 17:54:18 +00:00
|
|
|
SSE4_2_INSTRUCTION_LIST(EMIT_SSE34_AVXINSTR)
|
2016-09-12 06:24:06 +00:00
|
|
|
#undef EMIT_SSE34_AVXINSTR
|
|
|
|
|
|
2020-02-19 10:26:51 +00:00
|
|
|
#define EMIT_SSSE3_UNOP_AVXINSTR(instruction, notUsed1, notUsed2, notUsed3, \
|
|
|
|
|
notUsed4) \
|
|
|
|
|
__ v##instruction(xmm9, xmm3); \
|
|
|
|
|
__ v##instruction(xmm9, Operand(rdx, 5));
|
|
|
|
|
SSSE3_UNOP_INSTRUCTION_LIST(EMIT_SSSE3_UNOP_AVXINSTR)
|
|
|
|
|
#undef EMIT_SSSE3_UNOP_AVXINSTR
|
|
|
|
|
|
2020-01-06 18:51:23 +00:00
|
|
|
#define EMIT_SSE4_PMOV_AVXINSTR(instruction, notUsed1, notUsed2, notUsed3, \
|
|
|
|
|
notUsed4) \
|
|
|
|
|
__ v##instruction(xmm10, xmm1); \
|
|
|
|
|
__ v##instruction(xmm10, Operand(rdx, 4));
|
2020-02-27 08:45:39 +00:00
|
|
|
SSE4_UNOP_INSTRUCTION_LIST(EMIT_SSE4_PMOV_AVXINSTR)
|
2020-01-06 18:51:23 +00:00
|
|
|
#undef EMIT_SSE4_PMOV_AVXINSTR
|
|
|
|
|
|
2019-12-04 14:56:48 +00:00
|
|
|
#define EMIT_SSE2_SHIFT_IMM_AVX(instruction, notUsed1, notUsed2, notUsed3, \
|
|
|
|
|
notUsed4) \
|
|
|
|
|
__ v##instruction(xmm0, xmm15, 21);
|
|
|
|
|
SSE2_INSTRUCTION_LIST_SHIFT_IMM(EMIT_SSE2_SHIFT_IMM_AVX)
|
|
|
|
|
#undef EMIT_SSE2_SHIFT_IMM_AVX
|
|
|
|
|
|
2019-10-23 20:58:25 +00:00
|
|
|
__ vinsertps(xmm1, xmm2, xmm3, 1);
|
|
|
|
|
__ vinsertps(xmm1, xmm2, Operand(rbx, rcx, times_4, 10000), 1);
|
|
|
|
|
__ vextractps(rax, xmm1, 1);
|
|
|
|
|
|
2016-09-12 06:24:06 +00:00
|
|
|
__ vlddqu(xmm1, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ vpextrb(rax, xmm2, 12);
|
|
|
|
|
__ vpextrb(Operand(rbx, rcx, times_4, 10000), xmm2, 12);
|
|
|
|
|
__ vpextrw(rax, xmm2, 5);
|
|
|
|
|
__ vpextrw(Operand(rbx, rcx, times_4, 10000), xmm2, 5);
|
|
|
|
|
__ vpextrd(rax, xmm2, 2);
|
|
|
|
|
__ vpextrd(Operand(rbx, rcx, times_4, 10000), xmm2, 2);
|
2020-01-07 23:16:33 +00:00
|
|
|
__ vpextrq(rax, xmm2, 2);
|
2016-09-12 06:24:06 +00:00
|
|
|
|
|
|
|
|
__ vpinsrb(xmm1, xmm2, rax, 12);
|
|
|
|
|
__ vpinsrb(xmm1, xmm2, Operand(rbx, rcx, times_4, 10000), 12);
|
|
|
|
|
__ vpinsrw(xmm1, xmm2, rax, 5);
|
|
|
|
|
__ vpinsrw(xmm1, xmm2, Operand(rbx, rcx, times_4, 10000), 5);
|
|
|
|
|
__ vpinsrd(xmm1, xmm2, rax, 2);
|
|
|
|
|
__ vpinsrd(xmm1, xmm2, Operand(rbx, rcx, times_4, 10000), 2);
|
2019-12-04 11:15:11 +00:00
|
|
|
__ vpinsrq(xmm1, xmm2, rax, 9);
|
|
|
|
|
__ vpinsrq(xmm1, xmm2, Operand(rbx, rcx, times_4, 10000), 9);
|
2016-09-12 06:24:06 +00:00
|
|
|
__ vpshufd(xmm1, xmm2, 85);
|
2020-03-20 00:05:30 +00:00
|
|
|
__ vpshufd(xmm1, Operand(rbx, rcx, times_4, 10000), 85);
|
2019-12-02 09:20:32 +00:00
|
|
|
__ vpshuflw(xmm1, xmm2, 85);
|
|
|
|
|
__ vpshuflw(xmm1, Operand(rbx, rcx, times_4, 10000), 85);
|
2020-03-20 00:05:30 +00:00
|
|
|
__ vpshufhw(xmm1, xmm2, 85);
|
|
|
|
|
__ vpshufhw(xmm1, Operand(rbx, rcx, times_4, 10000), 85);
|
2019-10-19 00:44:25 +00:00
|
|
|
__ vshufps(xmm3, xmm2, xmm3, 3);
|
2019-12-09 09:17:33 +00:00
|
|
|
__ vpblendw(xmm1, xmm2, xmm3, 23);
|
|
|
|
|
__ vpblendw(xmm1, xmm2, Operand(rbx, rcx, times_4, 10000), 23);
|
2020-01-06 19:02:52 +00:00
|
|
|
__ vpalignr(xmm1, xmm2, xmm3, 4);
|
2019-12-02 09:20:32 +00:00
|
|
|
|
2020-01-10 17:54:44 +00:00
|
|
|
__ vblendvpd(xmm1, xmm2, xmm3, xmm4);
|
|
|
|
|
|
2019-12-04 11:15:11 +00:00
|
|
|
__ vmovddup(xmm1, xmm2);
|
2019-12-02 09:20:32 +00:00
|
|
|
__ vmovddup(xmm1, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ vbroadcastss(xmm1, Operand(rbx, rcx, times_4, 10000));
|
2014-12-01 10:45:02 +00:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2014-11-26 05:31:41 +00:00
|
|
|
// FMA3 instruction
|
|
|
|
|
{
|
|
|
|
|
if (CpuFeatures::IsSupported(FMA3)) {
|
|
|
|
|
CpuFeatureScope scope(&assm, FMA3);
|
2020-01-02 23:24:28 +00:00
|
|
|
#define EMIT_FMA(instr, notUsed1, notUsed2, notUsed3, notUsed4, notUsed5, \
|
|
|
|
|
notUsed6) \
|
|
|
|
|
__ instr(xmm9, xmm10, xmm11); \
|
|
|
|
|
__ instr(xmm9, xmm10, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
FMA_INSTRUCTION_LIST(EMIT_FMA)
|
|
|
|
|
#undef EMIT_FMA
|
2014-11-26 05:31:41 +00:00
|
|
|
}
|
|
|
|
|
}
|
2015-04-08 07:15:51 +00:00
|
|
|
|
|
|
|
|
// BMI1 instructions
|
|
|
|
|
{
|
|
|
|
|
if (CpuFeatures::IsSupported(BMI1)) {
|
|
|
|
|
CpuFeatureScope scope(&assm, BMI1);
|
|
|
|
|
__ andnq(rax, rbx, rcx);
|
|
|
|
|
__ andnq(rax, rbx, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ andnl(rax, rbx, rcx);
|
|
|
|
|
__ andnl(rax, rbx, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ bextrq(rax, rbx, rcx);
|
|
|
|
|
__ bextrq(rax, Operand(rbx, rcx, times_4, 10000), rbx);
|
|
|
|
|
__ bextrl(rax, rbx, rcx);
|
|
|
|
|
__ bextrl(rax, Operand(rbx, rcx, times_4, 10000), rbx);
|
|
|
|
|
__ blsiq(rax, rbx);
|
|
|
|
|
__ blsiq(rax, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ blsil(rax, rbx);
|
|
|
|
|
__ blsil(rax, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ blsmskq(rax, rbx);
|
|
|
|
|
__ blsmskq(rax, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ blsmskl(rax, rbx);
|
|
|
|
|
__ blsmskl(rax, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ blsrq(rax, rbx);
|
|
|
|
|
__ blsrq(rax, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ blsrl(rax, rbx);
|
|
|
|
|
__ blsrl(rax, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ tzcntq(rax, rbx);
|
|
|
|
|
__ tzcntq(rax, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ tzcntl(rax, rbx);
|
|
|
|
|
__ tzcntl(rax, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// LZCNT instructions
|
|
|
|
|
{
|
|
|
|
|
if (CpuFeatures::IsSupported(LZCNT)) {
|
|
|
|
|
CpuFeatureScope scope(&assm, LZCNT);
|
|
|
|
|
__ lzcntq(rax, rbx);
|
|
|
|
|
__ lzcntq(rax, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ lzcntl(rax, rbx);
|
|
|
|
|
__ lzcntl(rax, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// POPCNT instructions
|
|
|
|
|
{
|
|
|
|
|
if (CpuFeatures::IsSupported(POPCNT)) {
|
|
|
|
|
CpuFeatureScope scope(&assm, POPCNT);
|
|
|
|
|
__ popcntq(rax, rbx);
|
|
|
|
|
__ popcntq(rax, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ popcntl(rax, rbx);
|
|
|
|
|
__ popcntl(rax, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// BMI2 instructions
|
|
|
|
|
{
|
|
|
|
|
if (CpuFeatures::IsSupported(BMI2)) {
|
|
|
|
|
CpuFeatureScope scope(&assm, BMI2);
|
|
|
|
|
__ bzhiq(rax, rbx, rcx);
|
|
|
|
|
__ bzhiq(rax, Operand(rbx, rcx, times_4, 10000), rbx);
|
|
|
|
|
__ bzhil(rax, rbx, rcx);
|
|
|
|
|
__ bzhil(rax, Operand(rbx, rcx, times_4, 10000), rbx);
|
|
|
|
|
__ mulxq(rax, rbx, rcx);
|
|
|
|
|
__ mulxq(rax, rbx, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ mulxl(rax, rbx, rcx);
|
|
|
|
|
__ mulxl(rax, rbx, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ pdepq(rax, rbx, rcx);
|
|
|
|
|
__ pdepq(rax, rbx, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ pdepl(rax, rbx, rcx);
|
|
|
|
|
__ pdepl(rax, rbx, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ pextq(rax, rbx, rcx);
|
|
|
|
|
__ pextq(rax, rbx, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ pextl(rax, rbx, rcx);
|
|
|
|
|
__ pextl(rax, rbx, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ sarxq(rax, rbx, rcx);
|
|
|
|
|
__ sarxq(rax, Operand(rbx, rcx, times_4, 10000), rbx);
|
|
|
|
|
__ sarxl(rax, rbx, rcx);
|
|
|
|
|
__ sarxl(rax, Operand(rbx, rcx, times_4, 10000), rbx);
|
|
|
|
|
__ shlxq(rax, rbx, rcx);
|
|
|
|
|
__ shlxq(rax, Operand(rbx, rcx, times_4, 10000), rbx);
|
|
|
|
|
__ shlxl(rax, rbx, rcx);
|
|
|
|
|
__ shlxl(rax, Operand(rbx, rcx, times_4, 10000), rbx);
|
|
|
|
|
__ shrxq(rax, rbx, rcx);
|
|
|
|
|
__ shrxq(rax, Operand(rbx, rcx, times_4, 10000), rbx);
|
|
|
|
|
__ shrxl(rax, rbx, rcx);
|
|
|
|
|
__ shrxl(rax, Operand(rbx, rcx, times_4, 10000), rbx);
|
|
|
|
|
__ rorxq(rax, rbx, 63);
|
|
|
|
|
__ rorxq(rax, Operand(rbx, rcx, times_4, 10000), 63);
|
|
|
|
|
__ rorxl(rax, rbx, 31);
|
|
|
|
|
__ rorxl(rax, Operand(rbx, rcx, times_4, 10000), 31);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2014-07-30 13:54:45 +00:00
|
|
|
// xchg.
|
|
|
|
|
{
|
2016-05-19 00:55:08 +00:00
|
|
|
__ xchgb(rax, Operand(rax, 8));
|
|
|
|
|
__ xchgw(rax, Operand(rbx, 8));
|
2014-07-30 13:54:45 +00:00
|
|
|
__ xchgq(rax, rax);
|
|
|
|
|
__ xchgq(rax, rbx);
|
|
|
|
|
__ xchgq(rbx, rbx);
|
|
|
|
|
__ xchgq(rbx, Operand(rsp, 12));
|
|
|
|
|
}
|
|
|
|
|
|
2016-05-19 00:55:08 +00:00
|
|
|
// cmpxchg.
|
|
|
|
|
{
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|
|
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__ cmpxchgb(Operand(rsp, 12), rax);
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|
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__ cmpxchgw(Operand(rbx, rcx, times_4, 10000), rax);
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__ cmpxchgl(Operand(rbx, rcx, times_4, 10000), rax);
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__ cmpxchgq(Operand(rbx, rcx, times_4, 10000), rax);
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}
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|
2020-01-20 17:33:17 +00:00
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// xadd.
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{
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__ xaddb(Operand(rsp, 12), rax);
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__ xaddw(Operand(rsp, 12), rax);
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__ xaddl(Operand(rsp, 12), rax);
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__ xaddq(Operand(rsp, 12), rax);
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__ xaddb(Operand(rbx, rcx, times_4, 10000), rax);
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|
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__ xaddw(Operand(rbx, rcx, times_4, 10000), rax);
|
|
|
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__ xaddl(Operand(rbx, rcx, times_4, 10000), rax);
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|
|
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__ xaddq(Operand(rbx, rcx, times_4, 10000), rax);
|
|
|
|
|
}
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|
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|
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|
2016-05-19 00:55:08 +00:00
|
|
|
// lock prefix.
|
|
|
|
|
{
|
|
|
|
|
__ lock();
|
|
|
|
|
__ cmpxchgl(Operand(rsp, 12), rbx);
|
|
|
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|
|
|
|
|
__ lock();
|
|
|
|
|
__ xchgw(rax, Operand(rcx, 8));
|
|
|
|
|
}
|
|
|
|
|
|
2011-12-05 08:58:01 +00:00
|
|
|
// Nop instructions
|
|
|
|
|
for (int i = 0; i < 16; i++) {
|
|
|
|
|
__ Nop(i);
|
|
|
|
|
}
|
|
|
|
|
|
2019-07-18 09:10:30 +00:00
|
|
|
__ mfence();
|
|
|
|
|
__ lfence();
|
2018-05-09 15:02:15 +00:00
|
|
|
__ pause();
|
2011-12-05 08:58:01 +00:00
|
|
|
__ ret(0);
|
|
|
|
|
|
|
|
|
|
CodeDesc desc;
|
2017-05-31 14:00:11 +00:00
|
|
|
assm.GetCode(isolate, &desc);
|
2019-04-29 16:15:47 +00:00
|
|
|
Handle<Code> code = Factory::CodeBuilder(isolate, desc, Code::STUB).Build();
|
2014-04-16 11:50:24 +00:00
|
|
|
USE(code);
|
2011-12-05 08:58:01 +00:00
|
|
|
#ifdef OBJECT_PRINT
|
2018-06-14 12:46:07 +00:00
|
|
|
StdoutStream os;
|
2018-07-12 10:06:42 +00:00
|
|
|
code->Print(os);
|
2018-04-13 22:28:05 +00:00
|
|
|
Address begin = code->raw_instruction_start();
|
|
|
|
|
Address end = code->raw_instruction_end();
|
|
|
|
|
disasm::Disassembler::Disassemble(stdout, reinterpret_cast<byte*>(begin),
|
|
|
|
|
reinterpret_cast<byte*>(end));
|
2011-12-05 08:58:01 +00:00
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#undef __
|
2017-08-11 11:22:28 +00:00
|
|
|
|
|
|
|
|
} // namespace internal
|
|
|
|
|
} // namespace v8
|
