Commit Graph

35 Commits

Author SHA1 Message Date
erik.corry@gmail.com
d5738c0e6d Add ldrd and strd instructions to the ARM port. This is a
commit for zhangk@codeaurora.org.  See
http://codereview.chromium.org/568029 and
http://codereview.chromium.org/2019003

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4618 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-05-07 20:02:57 +00:00
erik.corry@gmail.com
6a03e12123 Allow unaligned memory accesses on ARM targets that support it.
The build process must add -DCAN_USE_UNALIGNED_ACCESSES=1 to the
C++ flags to activate the support.  This is a commit for
Subrato of CodeAurora.  See http://codereview.chromium.org/1731013
Small edits by Erik Corry to activate unaligned accesses by
default on the simulator and testing Android builds.


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4604 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-05-06 12:49:12 +00:00
erik.corry@gmail.com
a63d2bcd8d Put the icache checks in the ARM simulator behind a flag,
off by default, to speed up debug mode.
Review URL: http://codereview.chromium.org/1787006

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4521 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-04-28 07:15:34 +00:00
erik.corry@gmail.com
5fab20edcd Add checks to the ARM simulator to ensure that we flush the icache all
the places we should.
Review URL: http://codereview.chromium.org/1523030

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4474 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-04-22 12:41:10 +00:00
erik.corry@gmail.com
e1b3b92a2c Make not sucking at regexp the default
(remove V8_NATIVE_REGEXP flag, add
V8_INTERPRETED_REGEXP flag).
Review URL: http://codereview.chromium.org/1635001

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4443 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-04-19 19:30:11 +00:00
sgjesse@chromium.org
09aa20da08 Ensure stack alignment in ARM port
In the CEntryStub keep track of the actual skew from the correct alignment to ensure proper alignment before calling the runtime. Add checks to test the expected skew when running on hardware.

Use the PrepareCallCFunction/CallCFunction in a few other places.

Add check to the ARM simulator for correct alignment.

Add option --sim-stack-alignment to set the stack alignment in the simulator. Currntly only values 4 and 8 makes sense. 8 is the default to make snapshots generated with the simulator work on hardware requiring 8 byte stack alignment.
Review URL: http://codereview.chromium.org/1530043

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4425 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-04-15 09:34:47 +00:00
sgjesse@chromium.org
2239d42073 Fix presubmit error in previous commit.
TBR=erik.corry@gmail.com
Review URL: http://codereview.chromium.org/1640005

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4389 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-04-12 13:15:39 +00:00
sgjesse@chromium.org
8ebae39893 Add commands stack and mem to ARM simulator debugger
The command "stack" will dump the stack and "mem" will dump memory from a address given either as a register or as a literal. Both commands dump 10 words unless an additional argument with the number of words to dump is given.
  sim> stack
  sim> mem fp
  sim> mem 0xe612a450 100

Also parse address literals in simulator debugger command as unsigned.
Review URL: http://codereview.chromium.org/1596022

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4388 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-04-12 12:24:14 +00:00
erik.corry@gmail.com
cfad01282c Make binary op stubs in both r0-r1 and r1-r0 versions to reduce
register churn.
Review URL: http://codereview.chromium.org/1606019

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4380 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-04-09 18:25:51 +00:00
sgjesse@chromium.org
de69f5beba Add support for bkpt instruction
The bkpt instruction is now supported by both the disassembler and the simulator. In the simulator it breaks to the native debugger if any like int3 on Intel.

Moved the handling of the miscellaneous instructions to a separate part.

Review URL: http://codereview.chromium.org/1576026


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4360 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-04-08 13:30:48 +00:00
vegorov@chromium.org
b7833cb5f1 Port of optimized ICs for external and pixel arrays from ia32 to ARM.
Review URL: http://codereview.chromium.org/993002

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4228 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-03-23 13:38:04 +00:00
sgjesse@chromium.org
2618422ed5 ARMv7 ubfx support
Patch from Kun Zhang <zhangk@codeaurora.org>, see http://codereview.chromium.org/569015.
Review URL: http://codereview.chromium.org/573027

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3804 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-02-05 08:46:41 +00:00
lrn@chromium.org
f0ef4d7bac ARM: Implement native substring copying.
Review URL: http://codereview.chromium.org/552186

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3793 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-02-04 09:11:43 +00:00
whesse@chromium.org
f88e7e82b7 Add vstr and vldr floating point load and store to ARM assembler, disassembler, and simulator.
Review URL: http://codereview.chromium.org/545155

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3687 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-01-25 11:54:10 +00:00
sgjesse@chromium.org
ef0743abd7 Trace command in ARM simulator debugger
The ARM simulator debugger now has a 'trace' command which is used to toggle the trace of executed instructions.
Review URL: http://codereview.chromium.org/548068

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3632 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-01-18 14:11:37 +00:00
erik.corry@gmail.com
a5ac66628d Small optimization of ARM compare stub. Reverse all references to
left and right sides of the comparison to reflect reality.  Don't
check explicitly for NaNs when using VFP3 since the compare
operation can signal this case with the v flag.  Use cmp instead
of tst in the fast compilers since tst leaves the v flag unchanged
and thus can only work by accident on non-equality comparisons.
Review URL: http://codereview.chromium.org/551048

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3625 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-01-18 08:36:06 +00:00
erik.corry@gmail.com
593c388b39 Fix for bug 512 from Subrato De, CodeAurora.
Review URL: http://codereview.chromium.org/464016

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3435 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-12-09 11:14:45 +00:00
erik.corry@gmail.com
407816af39 Fix some style issues in the ARM code.
Also move a function into the macro assembler.
Fix some *& placement errors that had accumulated.
Review URL: http://codereview.chromium.org/385069

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3293 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-11-12 13:55:21 +00:00
erik.corry@gmail.com
0d94d7c785 Add vfp support on ARM. Patch from John Jozwiak.
Review URL: http://codereview.chromium.org/348019

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3292 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-11-12 13:04:02 +00:00
ager@chromium.org
b5a19c1036 Rework the way we handle the fact that the ARM simulator uses a
separate JS stack.

In exception handling, we need to be able to compare addresses into
the JavaScript portion of the stack with the address of a C++ handler
on the stack.  Since the stacks are separate on the simulator, we need
a JavaScript stack address corresponding to a C++ try catch handler in
order to perform valid address comparisons.

On the simulator, we now link the C++ try catch handlers indirectly
through the JS stack and use the JS stack indirection address for
comparisons.

      JS                    C++
                           
                           handler
 [C++ address]   <------    next_
                \
                 \
                  \---->   handler
 [C++ address]   <------    next_


On actual hardware the C++ try catch handlers continue to be directly
linked.

BUG=http://code.google.com/p/v8/issues/detail?id=271
Review URL: http://codereview.chromium.org/360004

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3228 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-11-05 13:27:21 +00:00
erik.corry@gmail.com
f2de3fd6d2 Fix the stack limits setting API so it is usable.
Review URL: http://codereview.chromium.org/242074

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3005 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-10-01 10:33:05 +00:00
sgjesse@chromium.org
3546e91bbc Refactor the register to name mapping in the ARM simulator.
Review URL: http://codereview.chromium.org/195024

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2847 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-09-09 07:01:20 +00:00
ager@chromium.org
5b3ce10995 Fix lint issue.
Review URL: http://codereview.chromium.org/197006

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2819 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-09-03 07:23:22 +00:00
sgjesse@chromium.org
8150609edb Fix the debugger in the ARM simulator.
The debugger in the ARM simulator is now working again.

Added a help command and a command to print all registers. Made the printobject command print something in release builds.
Review URL: http://codereview.chromium.org/191004

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2818 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-09-02 14:46:40 +00:00
lrn@chromium.org
9230ad29eb ARM native regexps.
Review URL: http://codereview.chromium.org/173567


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2785 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-08-31 12:40:37 +00:00
sgjesse@chromium.org
46a9b8f26b Make ARM simulator compile on Windows.
Remove suspicious line from ARM simulator, which caused a compiler warning on Windows.
Review URL: http://codereview.chromium.org/173464

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2756 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-08-26 08:11:46 +00:00
kasperl@chromium.org
94c4760225 Revert r2486, r2487, and r2488 until I get the chance to fix
the performance issue with number dictionaries.

TBR=kmillikin@chromium.org

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2490 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-07-17 04:57:17 +00:00
bak@chromium.org
e0047e4331 Changed hash table to use more of the hash value when probing.
Review URL: http://codereview.chromium.org/155350

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2486 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-07-16 12:56:50 +00:00
iposva@chromium.org
05b7b265cb - Update comments and fix a small glitch in the ARM disassembler.
- Fix the use of OS::ActivationFrameAlignment() when running with
  the simulator.
Review URL: http://codereview.chromium.org/155109

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2401 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-07-08 22:13:42 +00:00
erik.corry@gmail.com
9dd35ee2f9 ARM improvements to constant div, mod and mul.
* Fast runtime calls for div and mod.
* Fix assembly and disassembly of multiply instructions.
* Strength reduce and inline multiplications to shift-add.
* Strength reduce and inline mod by power of 2.
* Strength reduce mod by other small integers to mul.
* Strength reduce div by 2 and 3.
Review URL: http://codereview.chromium.org/155047

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2355 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-07-03 12:44:31 +00:00
erik.corry@gmail.com
cea9476cf0 More changes to make the simulator run code that is for the ARM5 snapshot.
Review URL: http://codereview.chromium.org/150100

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2307 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-06-30 13:38:40 +00:00
erik.corry@gmail.com
c9e004a808 Add a compare stub on ARM.
Review URL: http://codereview.chromium.org/151003

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2295 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-06-29 13:52:13 +00:00
erik.corry@gmail.com
6b2a49ff83 * Modify simulator and ARM code generator to avoid swi
instructions.  The intention is that the snapshots generated
by the simulator should be usable on the hardware.  Instead of
swi instructions we generate a branch to a swi instruction that
is not part of the snapshot.  The call/jump is patched up in
the same way as other external references when the snapshot
is deserialized.  This only works for EABI targets: on old ABI
targets we still emit some instructions not supported by the
simulator (fp coprocessor instructions).
Review URL: http://codereview.chromium.org/119036

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2127 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-06-09 09:26:53 +00:00
mikhail.naganov@gmail.com
30a0a7de43 Split nested namespaces declaration in two lines in accordance with C++ Style Guide.
This issue was raised by Brett Wilson while reviewing my changelist for readability. Craig Silverstein (one of C++ SG maintainers) confirmed that we should declare one namespace per line. Our way of namespaces closing seems not violating style guides (there is no clear agreement on it), so I left it intact.

Review URL: http://codereview.chromium.org/115756


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2038 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-05-25 10:05:56 +00:00
lrn@chromium.org
a4d756a1c8 Move backend specific files to separate directories.
Move ia32 and arm specific files to subdirectories to make it easier to add more backends.

Review URL: http://codereview.chromium.org/92068


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@1782 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-04-23 12:06:38 +00:00