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74 Commits

Author SHA1 Message Date
bmeurer@chromium.org
d07a2eb806 Rename ASSERT* to DCHECK*. 
This way we don't clash with the ASSERT* macros
defined by GoogleTest, and we are one step closer
to being able to replace our homegrown base/ with
base/ from Chrome.

R=jochen@chromium.org, svenpanne@chromium.org

Review URL: https://codereview.chromium.org/430503007

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22812 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-08-04 11:34:54 +00:00
danno@chromium.org
a1383e2250 Land the Fan (disabled) 
R=mstarzinger@chromium.org

Review URL: https://codereview.chromium.org/426233002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22709 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-07-30 13:54:45 +00:00
jochen@chromium.org
a4506cd3f2 Move platform abstraction to base library 
Also split v8-core independent methods from checks.h to base/logging.h and
merge v8checks with the rest of checks.

The CPU::FlushICache method is moved to CpuFeatures::FlushICache

RoundUp and related methods are moved to base/macros.h

Remove all layering violations from src/libplatform

BUG=none
R=jkummerow@chromium.org
LOG=n

Review URL: https://codereview.chromium.org/358363002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22092 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-06-30 13:25:46 +00:00
mstarzinger@chromium.org
fec6e62dfb Check alpha-sorting of includes during presubmit. 
R=rossberg@chromium.org

Review URL: https://codereview.chromium.org/333013002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21894 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-06-20 08:40:11 +00:00
jochen@chromium.org
9c2019b25c Remove dependency on Vector from platform files 
Add wrappers to utils.h instead.

BUG=none
R=jkummerow@chromium.org
LOG=n

Review URL: https://codereview.chromium.org/328343003

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21846 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-06-13 16:43:27 +00:00
jochen@chromium.org
56a486c322 Use full include paths everywhere 
- this avoids using relative include paths which are forbidden by the style guide
- makes the code more readable since it's clear which header is meant
- allows for starting to use checkdeps

BUG=none
R=jkummerow@chromium.org, danno@chromium.org
LOG=n

Review URL: https://codereview.chromium.org/304153016

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21625 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-06-03 08:12:43 +00:00
bmeurer@chromium.org
d4b533d41b Bulk update of Google copyright headers in source files. 
R=svenpanne@chromium.org

Review URL: https://codereview.chromium.org/259183002

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@21035 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-04-29 06:42:26 +00:00
rmcilroy@chromium.org
3eb418df78 Fix fixed-point vcvt_f64_s32 immediate value encoding 
The (32 - fraction_bits) value should be encoded so that the least
significant bit is set to bit 5 and the four next bits to bits 0-3. Fix
the previously incorrect encoding. This bug did not cause behavioral
issues before, since in existing uses of the function the order of the
bits in the immediate value does not matter, as they are all 1.

BUG=3256
LOG=N
R=ulan@chromium.org

Review URL: https://codereview.chromium.org/223623003

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20508 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-04-04 11:12:40 +00:00
rodolph.perfetta@arm.com
d5753f27d9 ARM: fix assertions for uxtb and co. 
Allow operands with ROR #0. Behind the scene they are mapped to LSL #0.

BUG=v8:3209
LOG=N
R=ulan@chromium.org

Review URL: https://codereview.chromium.org/198053014

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20171 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-03-21 15:59:45 +00:00
m.m.capewell@googlemail.com
6c4178330d ARM: Fix Q register encoding 
Fix Q register encoding for registers other than Q0. Also, fix value in NeonSize
enumeration.

BUG=
R=ulan@chromium.org

Review URL: https://codereview.chromium.org/207523005

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20163 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-03-21 13:04:20 +00:00
rmcilroy@chromium.org
49627050d0 Avoid trying to decode the raw inline constant which is part of the aged code prologue. 
BUG=v8:3007
LOG=N
R=bmeurer@chromium.org

Review URL: https://codereview.chromium.org/88303003

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@18097 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-11-27 10:07:57 +00:00
bmeurer@chromium.org
609ed28111 Revert "ConstantPoolSizeAt() should return number of Instructions instead, otherwise, some of the code will be treated as constant pool when printing code in ARM disassembler." 
This reverts commit r16419 for breaking the ARM simulator tests.

TEST=mjsunit/regress/regress-2624
R=machenbach@chromium.org

Review URL: https://codereview.chromium.org/23531013

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@16441 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-08-30 08:16:04 +00:00
bmeurer@chromium.org
899ec323af ConstantPoolSizeAt() should return number of Instructions instead, otherwise, some of the code will be treated as constant pool when printing code in ARM disassembler. 
BUG=none

TEST=none
R=bmeurer@chromium.org

Review URL: https://codereview.chromium.org/23654005

Patch from Bangfu Tao <bangfu.tao@samsung.com>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@16419 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-08-29 11:49:46 +00:00
bmeurer@chromium.org
50f3a993e7 Fix compilation with recent MinGW64 versions. 
Don't check for WIN32 define. Use V8_OS_* macros whenever
possible, and if not use _WIN32.

BUG=v8:2300
R=yangguo@chromium.org

Review URL: https://codereview.chromium.org/23687003

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@16380 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-08-28 08:35:04 +00:00
m.m.capewell@googlemail.com
cc9398cd42 ARM: Make double registers low/high safe 
This patch prevents taking the low/high part of a double-precision VFP register that has no corresponding single-precision VFP registers.

BUG=none
TEST=Added to test-disasm-arm.cc, test-assembler-arm.cc

Review URL: https://codereview.chromium.org/19560003

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@15885 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-07-25 15:04:38 +00:00
rodolph.perfetta@gmail.com
762157d697 ARM: Implement memcpy using NEON. 
Add support for a few NEON and ARM SIMD instructions and use them for various
memcpy operations.

BUG=none
TEST=none

Review URL: https://chromiumcodereview.appspot.com/17858002

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@15602 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-07-10 15:32:39 +00:00
yangguo@chromium.org
02674ee414 Keep two empty lines between declarations for cpp files 
R=yangguo@chromium.org

Review URL: https://codereview.chromium.org/18509003

Patch from Haitao Feng <haitao.feng@intel.com>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@15510 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-07-05 09:52:11 +00:00
jkummerow@chromium.org
c7a9bffbcf Clean up the usage of V8_TARGET_ARCH_${arch} and V8_HOST_ARCH_${arch} 
R=jkummerow@chromium.org

Review URL: https://codereview.chromium.org/18037002

Patch from Haitao Feng <haitao.feng@intel.com>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@15391 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-06-28 15:34:48 +00:00
rodolph.perfetta@gmail.com
45ec481659 ARM: Smi refactoring and improvements. 
Refactoring:
 * consistent use of SmiTag/Untag
 * added a few Smi macros and helpers
Improvements
 * small optimisations (e.g. merging untag and cmp #0)
 * added fixed point to double conversion instructions for simpler conversions

More on the last point: a Smi can be seen as a fixed point number with the
a one bit fractional part. Fixed to double instructions allow us to convert
a Smi to a double without untagging.

BUG=none
TEST=none

Review URL: https://chromiumcodereview.appspot.com/15085026

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@14724 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-05-17 15:38:14 +00:00
yangguo@chromium.org
dca3698584 Fix ARM build. 
R=ulan@chromium.org
BUG=

Review URL: https://chromiumcodereview.appspot.com/13986003

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@14204 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-04-10 09:35:11 +00:00
yangguo@chromium.org
cba3446d41 Use PrintF instead of fprintf. 
R=sven@chromium.org
BUG=

Review URL: https://chromiumcodereview.appspot.com/13811020

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@14200 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-04-10 09:18:41 +00:00
ulan@chromium.org
d18e118f17 ARM: Fix disassembly of some VFP instructions with condition codes 
Previously, we would disassemble some VFP instructions like this:

  vmla.f64eq d16, d17, d18

This patch moves the condition to the right place:

  vmlaeq.f64 d16, d17, d18

Spotted by Rodolph Perfetta!

BUG=none

Review URL: https://chromiumcodereview.appspot.com/12335129
Patch from Hans Wennborg <hans@chromium.org>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13752 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-02-27 11:52:45 +00:00
ulan@chromium.org
87265114c4 Emit VMLS for multiply-subtract on ARM. 
BUG=none

Review URL: https://chromiumcodereview.appspot.com/12319113
Patch from Hans Wennborg <hans@chromium.org>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13748 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-02-27 10:24:40 +00:00
ulan@chromium.org
bed569b548 ARM: Make use of d16-d31 when available. 
Review URL: https://chromiumcodereview.appspot.com/11428137
Patch from Hans Wennborg <hans@chromium.org>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13484 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-01-23 16:29:48 +00:00
ulan@chromium.org
74492ab2d4 Emit VMLA for multiply-add on ARM 
Review URL: https://chromiumcodereview.appspot.com/11293061
Patch from Hans Wennborg <hans@chromium.org>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@12958 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2012-11-14 11:01:18 +00:00
ulan@chromium.org
d247c5e6c7 Change constant pool marker to be the unconditional, permanently undefined instruction. 
The previously-used instruction isn't guaranteed to always be undefined,
and the encoding used was conditional (failing the condition on an
undefined instruction is itself undefined and not guaranteed to
fault!). I would have like to use a more clever encoding (see bug 2963),
but we need the extra bits to encode the size of the constant pool.

BUG=security
R=ulan@chromium.org

Review URL: https://chromiumcodereview.appspot.com/11242002
Patch from JF Bastien <jfb@chromium.org>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@12791 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2012-10-22 15:25:17 +00:00
ulan@chromium.org
a86e897924 Simulate and disasm NOP on ARM 
R=ulan@chromium.org

Review URL: https://chromiumcodereview.appspot.com/11116011
Patch from JF Bastien <jfb@chromium.org>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@12737 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2012-10-15 15:42:09 +00:00
danno@chromium.org
08747c3a16 Support for SDIV and MLS ARM instructions, and implement DoModI using them. 
Also added support for the runtime detection to check if hardware supports SDIV/UDIV
Other new opportunities to exploit SDIV/UDIV will be done in separate issues.

Review URL: https://chromiumcodereview.appspot.com/10977051
Patch from Subrato K De <subratokde@codeaurora.org>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@12646 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2012-10-01 21:27:33 +00:00
danno@chromium.org
557e2cd90e Fix disasm assertions for undefined instructions. 
BUG=none
TEST=none

Review URL: https://chromiumcodereview.appspot.com/9228006
Patch from Martyn Capewell <m.m.capewell@googlemail.com>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10498 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2012-01-25 12:43:32 +00:00
erik.corry@gmail.com
70da367f6b More spelling changes. 
Review URL: http://codereview.chromium.org/9231009

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10407 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2012-01-16 12:38:59 +00:00
vitalyr@chromium.org
5b63bc1fe8 Static state cleanup: add more consts. 
R=vegorov@chromium.org

Review URL: http://codereview.chromium.org/7491052

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@8843 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-08-05 11:32:46 +00:00
sgjesse@chromium.org
9cc5b94c2e Correctly handle the constant pool in constant pool splitting test 
The constant pool was not taken into account in the test test-compiler/SplitConstantsInFullCompiler which caused random failures.

This also reverts the test code added in r8469 and r8471.

R=ricow@chromium.org

BUG=none
TEST=test-compiler/SplitConstantsInFullCompiler

Review URL: http://codereview.chromium.org//7308001

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@8520 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-07-04 08:57:43 +00:00
sgjesse@chromium.org
c4f28bf274 Temporarily add more test output to help locate test failure 
R=ricow@chromium.org

BUG=none
TEST=none

Review URL: http://codereview.chromium.org//7250002

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@8469 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-06-29 13:40:23 +00:00
karlklose@chromium.org
b606195012 ARM: Fix disasm for strh, vabs, vneg. Add load/store tests. 
Patch from ARM Ltd.

BUG=none
TEST=added to test/cctest/test-disasm-arm.cc

Original review at http://codereview.chromium.org/7013024/.

Review URL: http://codereview.chromium.org/7013027

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7875 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-05-12 14:44:49 +00:00
sgjesse@chromium.org
6255476028 ARM: Add support load/store multiple VFP registers 
Enter/exit frames with save doubles use these instructions instead of generating 16 load/store instructions.

R=karlklose@chromium.org, rodolph.perfetta@gmail.com

BUG=
TEST=

Review URL: http://codereview.chromium.org//6691057

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7509 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-04-06 09:06:23 +00:00
karlklose@chromium.org
e820926108 Improve ARM-Simulator. 
This patch
- removes the unimplemented code crash when rendering invalid/unknown instructions and prints "unknown" instead.
- prints the beginning of the constant pool marker.
- adds "da" as a shortcut for "disasm".
- print hexadecimal representation of double and single registers. This makes it easier to debug move/conversion code that uses temporary int32 values in floating point registers.
- annotates the stack with short prints of the values (HeapObjects and smis),
- makes disasm take an address or a register as second argument without a third argument, which defaults to printing ten instructions.

Review URL: http://codereview.chromium.org/6676042

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7279 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-21 09:59:58 +00:00
vitalyr@chromium.org
7976ca2cbc Merge isolates to bleeding_edge. 
git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7271 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-18 20:35:07 +00:00
vitalyr@chromium.org
76e226f832 Revert r7268: it borked the history. 
git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7269 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-18 19:41:05 +00:00
vitalyr@chromium.org
6ff7fdebd3 Merge isolates to bleeding_edge. 
Review URL: http://codereview.chromium.org/6685088

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7268 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-18 18:49:56 +00:00
karlklose@chromium.org
984135cb32 ARM: Improved double to integer truncation. 
Patch from ARM Ltd.

BUG=none
TEST=Added to cctest/test-assembler-arm.cc and cctest/test-disasm-arm.cc

Review URL: http://codereview.chromium.org/6625084

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7174 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-15 11:19:13 +00:00
ager@chromium.org
8198db7934 ARM: Add support for DoMathAbs with double inputs. 
Adds vabs instruction to simulator, assembler, disassembler and tests.

BUG=none
TEST=Added to cctest.

Review URL: http://codereview.chromium.org/6366016

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6531 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-01-31 10:16:28 +00:00
ager@chromium.org
0e183035a2 ARM: Merging constants in simulator and assembler header files and other cleanup. 
First stab at a general ARM cleanup patch. It merges ARM constants so that they can be used across simulator, assembler and disassembler, and tidies up some syntax and ambiguities.

BUG=none
TEST=none

Review URL: http://codereview.chromium.org/6274009

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6483 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-01-26 08:32:54 +00:00
erik.corry@gmail.com
ca7a438713 Improve support for vmrs/vmsr in ARM disassembler. This is a commit of http://codereview.chromium.org/4904001 for Martyn Capewell. 
git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5824 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-11-15 10:21:57 +00:00
ager@chromium.org
2122827893 Landing for Rodolph Perfetta. 
Fix the ARM simulator, the ARM disassembler and extend the stop feature. 
The stop feature in the simulator now support enabling, disabling and 
counting. 

BUG=None 
TEST=None 

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5723 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-10-28 07:35:07 +00:00
erik.corry@gmail.com
66d13be5f9 Fix incorrect encoding of single and double precision registers for some VFP instructions. Also fix incorrect disassembling of vldr/vstr. This is a commit of http://codereview.chromium.org/3107027 for Rodolph Perfetta. 
git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5352 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-08-26 08:53:00 +00:00
sgjesse@chromium.org
e61bd7bd26 ARM: backend opt for ToBoolean: JIT code generation for ToBool 
Upgraded the CodeGenerator::ToBoolean() function in the ARM backend to use complete JIT code generation and not make runtime calls to ToBool (when VFP is enabled). 

This change also includes the vcmp VFP instruction that supports a constant 0.0 as the second operand. 

Patch by Subrato K De <subratokde@codeaurora.org>



git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5267 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-08-16 07:52:49 +00:00
ager@chromium.org
74f9789f61 Landing for Rodolph Perfetta. 
Add support for saturation instruction (ARMv6 or above).
The byte array clamping code has been updated accordingly.

Review URL: http://codereview.chromium.org/3036008/show

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5106 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-07-21 07:42:51 +00:00
erik.corry@gmail.com
8c767e02f9 ARM: Add support for the VFP mov literal instruction and mov 
between single VFP registers.  Math.pow implementation has
been updated with the new instructions.  This is a commit
of http://codereview.chromium.org/2813046/show for Rodolph
Perfetta.


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5037 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-07-08 12:38:02 +00:00
sgjesse@chromium.org
ff6c4fe680 ARM: Special code for raising to the power of an integer 
When calculating Math.pow where the exponent is a smi use a simple loop to calculate the result.

Added support for the vmov instruction moving from one doubleword extension register to another.

Added some Math.pow tests which partially covers what is in the Sputnik tests.
Review URL: http://codereview.chromium.org/2804033

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4990 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-06-30 12:22:15 +00:00
sgjesse@chromium.org
65018d9123 ARM: Use the vsqrt instruction when available 
vsqrt is used to calculate Math.sqrt(x), Math.pow(x, 0.5) and Math.pow(x, -0.5). Code size doesn't matter, as %_MathSqrt and %_MathPow are only called in one place each.
Review URL: http://codereview.chromium.org/2885002

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4974 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-06-29 09:40:36 +00:00