AuroraMiddleware/v8
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96 Commits

Author SHA1 Message Date
bbudge
26ecb4a1d7 [Turbofan] Add ia32 support for 4 and 16 byte moves and swaps. 
- Adds move/swap handling for 4 and 16 bytes to ia32.
- Register allocator now only requests 4 bytes for floats on ia32 and arm.
- We probably need similar support in mips.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2027043002
Cr-Commit-Position: refs/heads/master@{#37714}
 2016-07-13 13:54:39 +00:00
ishell
d9e8764f81 [ic] Split LoadIC into LoadGlobalIC and LoadIC. 
The former will handle loads of predeclared global variables (vars and
functions), lets, consts and undeclared variables. The latter will handle
named loads from explicit receiver. In addition, named loads does not
depend of the TypeofMode.

TypeofMode related cleanup will be done in the follow-up CL.

BUG=chromium:576312
LOG=Y
TBR=bmeurer@chromium.org

Review-Url: https://codereview.chromium.org/1912633002
Cr-Commit-Position: refs/heads/master@{#36965}
 2016-06-14 13:21:28 +00:00
machenbach
479de28c3a Revert of Adding ia32 simd assembler changes. (patchset #2 id:20001 of https://codereview.chromium.org/1991713002/ ) 
Reason for revert:
Crashes on win32 debug:
https://build.chromium.org/p/client.v8/builders/V8%20Win32%20-%20debug/builds/2305/steps/Check/logs/stdio

Also, would be nice if the test output could be a bit shorter and only print what's necessary to trace a failure. Or split things into more smaller tests. Like that, these logs must be processed, json-encoded/decoded and sent around through the infrastructure.

Some chars in the output make the json encoder unhappy, therefore the infrastructure can't nicely display the failures.

Original issue's description:
> Adding ia32 simd assembler support.
>
> Based on assembler changes from this patch:
> https://codereview.chromium.org/90643003/
>
> BUG=https://bugs.chromium.org/p/v8/issues/detail?id=4124
> R=titzer@chromium.org
> LOG=N
>
> Committed: https://crrev.com/fbf58a5af1d07a7fbb3763aa15f8ba26e2ce7d11
> Cr-Commit-Position: refs/heads/master@{#36349}

TBR=bbudge@chromium.org,titzer@chromium.org,gdeepti@chromium.org,aseemgarg@chromium.org,bradnelson@chromium.org
# Skipping CQ checks because original CL landed less than 1 days ago.
NOPRESUBMIT=true
NOTREECHECKS=true
NOTRY=true
BUG=https://bugs.chromium.org/p/v8/issues/detail?id=4124

Review-Url: https://codereview.chromium.org/1992163002
Cr-Commit-Position: refs/heads/master@{#36353}
 2016-05-19 08:58:18 +00:00
bradnelson
fbf58a5af1 Adding ia32 simd assembler support. 
Based on assembler changes from this patch:
https://codereview.chromium.org/90643003/

BUG=https://bugs.chromium.org/p/v8/issues/detail?id=4124
R=titzer@chromium.org
LOG=N

Review-Url: https://codereview.chromium.org/1991713002
Cr-Commit-Position: refs/heads/master@{#36349}
 2016-05-19 08:04:10 +00:00
binji
5c22cf5ae7 Add cmpxchg and lock instructions to x64 and ia32 {dis,}assemblers 
Review-Url: https://codereview.chromium.org/1986113004
Cr-Commit-Position: refs/heads/master@{#36341}
 2016-05-19 00:56:08 +00:00
verwaest
911a5768dc Simplify IC interfaces 
BUG=

Review URL: https://codereview.chromium.org/1865873002

Cr-Commit-Position: refs/heads/master@{#35301}
 2016-04-06 13:38:33 +00:00
epertoso
22523f25b1 Extends testb and cmpb/cmpw instruction support in the ia32 assembler. 
This is in preparation for a CL that does the equivalent of http://crrev.com/1780193003 for ia32.

BUG=

Review URL: https://codereview.chromium.org/1815213002

Cr-Commit-Position: refs/heads/master@{#34925}
 2016-03-21 10:09:26 +00:00
ahaas
1b23079936 [wasm] Int64Lowering of Int64Add on ia32 and arm. 
Int64Add is lowered to a new turbofan operator, Int32AddPair. The new
operator takes 4 inputs an generates 2 outputs. The inputs are the low
word of the left input, high word of the left input, the low word of the
right input, and high word of the right input. The ouputs are the low
and high word of the result of the addition.

R=titzer@chromium.org, v8-arm-ports@googlegroups.com

Review URL: https://codereview.chromium.org/1778493004

Cr-Commit-Position: refs/heads/master@{#34747}
 2016-03-14 15:34:19 +00:00
ahaas
240b7db9c7 [wasm] Int64Lowering of I64ShrU and I64ShrS on ia32. 
I implemented I64ShrU and I64ShrS the same as I64Shl in https://codereview.chromium.org/1756863002

R=titzer@chromium.org

Review URL: https://codereview.chromium.org/1768233002

Cr-Commit-Position: refs/heads/master@{#34630}
 2016-03-09 16:38:43 +00:00
ahaas
ddc626e1cf [wasm] Int64Lowering of I64Shl on ia32. 
I64Shl is lowered to a new turbofan operator, WasmWord64Shl. The new
operator takes 3 inputs, the low-word input, the high-word input, and
the shift, and produces 2 output, the low-word output and the high-word
output.

At the moment I implemented the lowering only for ia32, but I think the
CL is already big enough. I will add the other platforms in separate
CLs.

R=titzer@chromium.org

Review URL: https://codereview.chromium.org/1756863002

Cr-Commit-Position: refs/heads/master@{#34546}
 2016-03-07 15:19:44 +00:00
jochen
6f472db65a Disable soon to be deprecated APIs per default for v8 
Embedders still can use those APIs by default

test-api.cc still has an exception to use the old APIs...

BUG=v8:4143
R=vogelheim@chromium.org
LOG=n

Review URL: https://codereview.chromium.org/1505803004

Cr-Commit-Position: refs/heads/master@{#32701}
 2015-12-09 10:35:04 +00:00
jochen
3cf6e040c4 Mark cctests that don't use deprecated APIs as such 
BUG=4134
R=epertoso@chromium.org
LOG=n

Review URL: https://codereview.chromium.org/1451733002

Cr-Commit-Position: refs/heads/master@{#32011}
 2015-11-16 16:45:31 +00:00
mstarzinger
19a49abf02 Realize IWYU pattern for frames-inl.h header. 
R=bmeurer@chromium.org

Review URL: https://codereview.chromium.org/1283183002

Cr-Commit-Position: refs/heads/master@{#30127}
 2015-08-12 10:28:47 +00:00
yangguo
1667c15e37 Debugger: move implementation to a separate folder. 
R=cbruni@chromium.org

Review URL: https://codereview.chromium.org/1265923002

Cr-Commit-Position: refs/heads/master@{#29951}
 2015-07-31 11:08:15 +00:00
ishell
fec3c9cba6 TypeofMode replaces TypeofState and ContextualMode. 
NON_CONTEXTUAL ~> INSIDE_TYPEOF
CONTEXTUAL ~> NOT_INSIDE_TYPEOF

Review URL: https://codereview.chromium.org/1227893005

Cr-Commit-Position: refs/heads/master@{#29611}
 2015-07-13 13:39:43 +00:00
Weiliang Lin
38e764f7ac [x86] Introduce vandps/vandpd/vxorps/vxorpd. 
R=bmeurer@chromium.org

Review URL: https://codereview.chromium.org/1072343002

Cr-Commit-Position: refs/heads/master@{#27768}
 2015-04-11 00:58:38 +00:00
jing.bao
dba47f6486 [ia32] Introduce BMI instructions. 
BUG=v8:4015
LOG=n

Review URL: https://codereview.chromium.org/1069683002

Cr-Commit-Position: refs/heads/master@{#27683}
 2015-04-09 06:50:58 +00:00
bmeurer
8dad78cdbd [turbofan] Add backend support for float32 operations. 
This adds the basics necessary to support float32 operations in TurboFan.
The actual functionality required to detect safe float32 operations will
be added based on this later. Therefore this does not affect production
code except for some cleanup/refactoring.

In detail, this patchset contains the following features:
- Add support for float32 operations to arm, arm64, ia32 and x64
  backends.
- Add float32 machine operators.
- Add support for float32 constants to simplified lowering.
- Handle float32 representation for phis in simplified lowering.

In addition, contains the following (related) cleanups:
- Fix/unify naming of backend instructions.
- Use AVX comparisons when available.
- Extend ArchOpcodeField to 9 bits (required for arm64).
- Refactor some code duplication in instruction selectors.

BUG=v8:3589
LOG=n
R=dcarney@chromium.org

Review URL: https://codereview.chromium.org/1044793002

Cr-Commit-Position: refs/heads/master@{#27509}
 2015-03-30 07:34:04 +00:00
yangguo
019096f829 Serializer: move to a subfolder and clean up includes. 
R=jochen@chromium.org

Review URL: https://codereview.chromium.org/1041743002

Cr-Commit-Position: refs/heads/master@{#27501}
 2015-03-27 15:29:07 +00:00
bmeurer
99f8d57f3c [turbofan] Introduce optional Float64Min and Float64Max machine operators. 
Basically recognize certain x < y ? x : y constructs and turn that into
Float64Min/Float64Max operations, if the target machine supports that.
On x86 we lower to (v)minsd/(v)maxsd.

R=dcarney@chromium.org

Review URL: https://codereview.chromium.org/998283002

Cr-Commit-Position: refs/heads/master@{#27160}
 2015-03-12 14:07:39 +00:00
bmeurer
4436c2642a [turbofan] Support for %_DoubleHi, %_DoubleLo and %_ConstructDouble. 
This adds support for the double bits intrinsics to TurboFan, and is
a first step towards fast Math functions inlined into TurboFan code
or even compiled by themselves with TurboFan.

Review URL: https://codereview.chromium.org/974313002

Cr-Commit-Position: refs/heads/master@{#27006}
 2015-03-05 09:22:38 +00:00
weiliang.lin
4f3d27e64f [ia32] Introduce FMA3 instructions on scalar data elements. 
port 83a635e0d7

BUG=

Review URL: https://codereview.chromium.org/773783002

Cr-Commit-Position: refs/heads/master@{#25619}
 2014-12-02 15:30:09 +00:00
weiliang.lin
2ad1c224b8 [ia32] Introduce vex prefix version of float64 arithmetic binop 
port 50c4d8826b

BUG=

Review URL: https://codereview.chromium.org/770183002

Cr-Commit-Position: refs/heads/master@{#25595}
 2014-12-02 08:09:53 +00:00
bmeurer@chromium.org
8c5fdd0575 IA: Double arithmetic binops support memory operand 
BUG=
R=dcarney@chromium.org

Review URL: https://codereview.chromium.org/662813002

Patch from Weiliang Lin <weiliang.lin@intel.com>.

Cr-Commit-Position: refs/heads/master@{#25052}
git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@25052 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-11-03 05:57:17 +00:00
dcarney@chromium.org
907ad65dce [turbofan]IA: ChangeFloat32ToFloat64 supports mem operand 
BUG=
R=titzer@chromium.org

Review URL: https://codereview.chromium.org/641153003

Patch from Jing Bao <jing.bao@intel.com>.

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24542 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-10-13 07:42:35 +00:00
dcarney@chromium.org
3396c2badd [turbofan] IA: TruncateFloat64ToFloat32 supports mem operand 
BUG=
R=dcarney@chromium.org

Review URL: https://codereview.chromium.org/639283003

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24541 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-10-13 07:12:57 +00:00
dcarney@chromium.org
e9fcaa4be9 [turbofan] support all shift operands on ia32 
R=bmeurer@chromium.org

BUG=

Review URL: https://codereview.chromium.org/619663002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24387 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-10-02 09:04:04 +00:00
titzer@chromium.org
8892385565 [turbofan] IA: Float64ToUint32 supports mem operand 
BUG=
R=titzer@chromium.org

Review URL: https://codereview.chromium.org/582713002

Patch from Weiliang Lin <weiliang.lin@intel.com>.

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24092 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-09-19 14:25:13 +00:00
verwaest@chromium.org
30c3981c2c Move IC code into a subdir and move ic-compilation related code from stub-cache into ic-compiler 
BUG=
R=bmeurer@chromium.org

Review URL: https://codereview.chromium.org/483683005

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@23306 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-08-22 11:43:39 +00:00
danno@chromium.org
a1383e2250 Land the Fan (disabled) 
R=mstarzinger@chromium.org

Review URL: https://codereview.chromium.org/426233002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22709 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-07-30 13:54:45 +00:00
svenpanne@chromium.org
018ef484b9 More OStreamsUse OStreams more often. 
This is a mostly mechanical CL (more than 90% Emacs macros and
query-replace-regexp) moving FILE*/StringStream*-based APIs to
OStream-based APIs. There are a few places where this had to stop,
otherwise the CL would be even bigger, but this can easily and
incrementally cleaned up later.

R=bmeurer@chromium.org

Review URL: https://codereview.chromium.org/363323003

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22232 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-07-07 09:57:29 +00:00
jochen@chromium.org
56a486c322 Use full include paths everywhere 
- this avoids using relative include paths which are forbidden by the style guide
- makes the code more readable since it's clear which header is meant
- allows for starting to use checkdeps

BUG=none
R=jkummerow@chromium.org, danno@chromium.org
LOG=n

Review URL: https://codereview.chromium.org/304153016

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21625 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-06-03 08:12:43 +00:00
yangguo@chromium.org
6fd69c2476 Remove special debug ExternalReferences. 
R=ulan@chromium.org

Review URL: https://codereview.chromium.org/296043002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21421 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-05-22 07:57:33 +00:00
yangguo@chromium.org
a7a6abbde6 Require CMOV support for the ia32 port. 
R=svenpanne@chromium.org

Review URL: https://codereview.chromium.org/275253004

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21279 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-05-13 08:16:26 +00:00
yangguo@chromium.org
3fa6100ed3 Require SSE2 support for the ia32 port. 
R=svenpanne@chromium.org

Review URL: https://codereview.chromium.org/275433004

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21223 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-05-09 13:01:50 +00:00
yangguo@chromium.org
cb2f43cb14 Always include debugger support. 
Motivation: we do not have test coverage for debuggersupport=off.

R=jkummerow@chromium.org

Review URL: https://codereview.chromium.org/256653004

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20969 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-04-25 11:00:37 +00:00
yangguo@chromium.org
5e02daca21 Fix unused variable warnings. 
TBR=jarin@chromium.org

Review URL: https://codereview.chromium.org/238543008

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20797 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-04-16 11:50:24 +00:00
yangguo@chromium.org
17b33fa1da Handlify code allocation. 
R=mstarzinger@chromium.org

Review URL: https://codereview.chromium.org/235153003

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20795 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-04-16 11:38:56 +00:00
mstarzinger@chromium.org
9ab32061ed Print properly signed displacement in disassembler. 
R=titzer@chromium.org
BUG=

Review URL: https://codereview.chromium.org/178193028

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@19667 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-03-05 09:28:26 +00:00
yangguo@chromium.org
6f95c0b11b [x64] add disasm for two fp instructions 
BUG=
R=yangguo@chromium.org

Review URL: https://codereview.chromium.org/146583002

Patch from Weiliang Lin <weiliang.lin@intel.com>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@19022 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-02-03 08:13:12 +00:00
mvstanton@chromium.org
e3e7daf01c We need to know if a load, store or call IC is assumed 
to be on the global object. Previously, this information
was stored in RelocInfo. A more logical place for this kind
of structural information is ExtraICState. Storing it there
makes it easier for us to gather type feedback from these
sites too.

R=verwaest@chromium.org

Review URL: https://codereview.chromium.org/96083005

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@18466 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-01-07 14:14:34 +00:00
svenpanne@chromium.org
c524efd759 Introduce addps/subps/mulps/divps for IA32/X64 
BUG=
R=svenpanne@chromium.org

Review URL: https://codereview.chromium.org/60093005

Patch from Weiliang Lin <weiliang.lin@intel.com>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@17842 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-11-18 15:24:41 +00:00
svenpanne@chromium.org
74ad230a8e Introduce orps for IA32/X64 
BUG=
R=svenpanne@chromium.org

Review URL: https://codereview.chromium.org/53573004

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@17479 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-11-05 12:04:46 +00:00
svenpanne@chromium.org
19a2e803bb Introduce andps for IA32/X64 
replace andpd and pand in Math.abs

BUG=
R=svenpanne@chromium.org

Review URL: https://codereview.chromium.org/44153002

Patch from Weiliang Lin <weiliang.lin@intel.com>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@17413 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-10-28 10:38:40 +00:00
jkummerow@chromium.org
4e96d4dee6 Tweak Math.log on ia32/x64 
ia32 and x64 more consistent now
1. use non-transcendental cache version of log for x64
2. use negative infinity constant instead of pushing to stack and loading to XMM register
3. remove movdbl, use movsd directly. movdbl seems confusing

BUG=
R=jkummerow@chromium.org

Review URL: https://codereview.chromium.org/27197013

Patch from Weiliang Lin <weiliang.lin2@gmail.com>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@17268 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-10-18 10:54:45 +00:00
svenpanne@chromium.org
258cee8f72 Fixed bug in extractps instruction on ia32 and x64 
This is a fixed version of https://codereview.chromium.org/27097002/
which was originally written by weiliang.lin@intel.com.

R=bmeurer@chromium.org

Review URL: https://codereview.chromium.org/27301003

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@17217 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-10-15 12:51:58 +00:00
bmeurer@chromium.org
5768fcf12c Fix the CPU feature detection. 
Move all of the CPU detection logic to the CPU class, and make
all other code use the CPU class for feature detection.

This also fixes the ARM CPU feature detection logic, which was
based on fragile string search in /proc/cpuinfo. Now we use
ELF hwcaps if available, falling back to sane(!!) parsing of
/proc/cpuinfo for CPU features.

The ia32 and x64 code was also cleaned up to make it usable
outside the assembler.

R=svenpanne@chromium.org

Review URL: https://codereview.chromium.org/23401002

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@16315 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-08-26 09:37:39 +00:00
bmeurer@chromium.org
ee718489fe Drop unused rdtsc instruction. 
We do not use rdtsc anywhere and we won't ever use that in the
future, as it is totally unusable with multicore and out of
order execution.

R=jkummerow@chromium.org

Review URL: https://codereview.chromium.org/23112016

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@16268 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-08-22 11:58:20 +00:00
mstarzinger@chromium.org
f8db2414f2 Deprecate FACTORY helper macro. 
This removes the FACTORY helper macro to avoid accidental TLS access
when using the factory. Most internal code has access to the Isolate by
now whereas tests which are not performance critical still heavily use
TLS access through explicit Isolate::Current() calls.

R=svenpanne@chromium.org

Review URL: https://codereview.chromium.org/16337005

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@14931 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-06-04 10:30:05 +00:00
dcarney@chromium.org
ff2a76b5d5 remove most V8_ALLOW_ACCESS_TO_* defines from test classes 
R=svenpanne@chromium.org
BUG=

Review URL: https://codereview.chromium.org/15964004

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@14849 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-05-28 11:54:52 +00:00