2009-05-06 12:08:50 +00:00
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// Copyright (c) 1994-2006 Sun Microsystems Inc.
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// All Rights Reserved.
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//
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2009-05-04 07:16:10 +00:00
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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2009-05-06 12:08:50 +00:00
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// - Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// - Redistribution in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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2009-05-04 07:16:10 +00:00
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//
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2009-05-06 12:08:50 +00:00
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// - Neither the name of Sun Microsystems or the names of contributors may
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// be used to endorse or promote products derived from this software without
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// specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// The original source code covered by the above license above has been
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// modified significantly by Google Inc.
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// Copyright 2006-2009 the V8 project authors. All rights reserved.
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// A lightweight X64 Assembler.
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2009-05-04 07:16:10 +00:00
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2009-05-05 14:39:05 +00:00
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#ifndef V8_X64_ASSEMBLER_X64_H_
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#define V8_X64_ASSEMBLER_X64_H_
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2009-05-25 10:05:56 +00:00
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namespace v8 {
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namespace internal {
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2009-05-05 14:39:05 +00:00
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2009-06-03 10:30:50 +00:00
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// Utility functions
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// Test whether a 64-bit value is in a specific range.
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static inline bool is_uint32(int64_t x) {
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2009-08-03 11:05:26 +00:00
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static const int64_t kUInt32Mask = V8_INT64_C(0xffffffff);
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2009-06-19 09:12:20 +00:00
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return x == (x & kUInt32Mask);
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2009-06-03 10:30:50 +00:00
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}
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static inline bool is_int32(int64_t x) {
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2009-08-03 11:05:26 +00:00
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static const int64_t kMinIntValue = V8_INT64_C(-0x80000000);
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2009-06-03 10:30:50 +00:00
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return is_uint32(x - kMinIntValue);
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2009-08-03 11:05:26 +00:00
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}
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static inline bool uint_is_int32(uint64_t x) {
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static const uint64_t kMaxIntValue = V8_UINT64_C(0x80000000);
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return x < kMaxIntValue;
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}
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static inline bool is_uint32(uint64_t x) {
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static const uint64_t kMaxUIntValue = V8_UINT64_C(0x100000000);
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return x < kMaxUIntValue;
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2009-06-03 10:30:50 +00:00
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}
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2009-05-06 12:08:50 +00:00
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// CPU Registers.
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//
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// 1) We would prefer to use an enum, but enum values are assignment-
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// compatible with int, which has caused code-generation bugs.
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//
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// 2) We would prefer to use a class instead of a struct but we don't like
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// the register initialization to depend on the particular initialization
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// order (which appears to be different on OS X, Linux, and Windows for the
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// installed versions of C++ we tried). Using a struct permits C-style
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// "initialization". Also, the Register objects cannot be const as this
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// forces initialization stubs in MSVC, making us dependent on initialization
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// order.
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//
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// 3) By not using an enum, we are possibly preventing the compiler from
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// doing certain constant folds, which may significantly reduce the
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// code generated for some assembly instructions (because they boil down
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// to a few constants). If this is a problem, we could change the code
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// such that we use an enum in optimized mode, and the struct in debug
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// mode. This way we get the compile-time error checking in debug mode
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// and best performance in optimized code.
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//
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2009-05-05 14:39:05 +00:00
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struct Register {
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2009-05-28 09:18:17 +00:00
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static Register toRegister(int code) {
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2009-06-10 09:48:15 +00:00
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Register r = { code };
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2009-05-28 09:18:17 +00:00
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return r;
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}
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2009-05-27 07:53:47 +00:00
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bool is_valid() const { return 0 <= code_ && code_ < 16; }
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2009-05-05 14:39:05 +00:00
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bool is(Register reg) const { return code_ == reg.code_; }
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int code() const {
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ASSERT(is_valid());
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return code_;
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}
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int bit() const {
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2009-06-10 09:48:15 +00:00
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return 1 << code_;
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2009-05-05 14:39:05 +00:00
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}
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2009-06-22 08:17:44 +00:00
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// Return the high bit of the register code as a 0 or 1. Used often
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// when constructing the REX prefix byte.
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int high_bit() const {
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return code_ >> 3;
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}
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// Return the 3 low bits of the register code. Used when encoding registers
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// in modR/M, SIB, and opcode bytes.
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int low_bits() const {
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return code_ & 0x7;
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}
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2009-06-10 09:48:15 +00:00
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// (unfortunately we can't make this private in a struct when initializing
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// by assignment.)
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2009-05-05 14:39:05 +00:00
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int code_;
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};
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2009-05-06 12:08:50 +00:00
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extern Register rax;
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extern Register rcx;
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extern Register rdx;
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extern Register rbx;
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extern Register rsp;
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extern Register rbp;
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extern Register rsi;
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extern Register rdi;
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extern Register r8;
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extern Register r9;
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extern Register r10;
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extern Register r11;
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extern Register r12;
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extern Register r13;
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extern Register r14;
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extern Register r15;
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2009-05-05 14:39:05 +00:00
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extern Register no_reg;
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2009-06-17 11:50:33 +00:00
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struct MMXRegister {
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bool is_valid() const { return 0 <= code_ && code_ < 2; }
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int code() const {
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ASSERT(is_valid());
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return code_;
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}
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int code_;
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};
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extern MMXRegister mm0;
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extern MMXRegister mm1;
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extern MMXRegister mm2;
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extern MMXRegister mm3;
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extern MMXRegister mm4;
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extern MMXRegister mm5;
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extern MMXRegister mm6;
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extern MMXRegister mm7;
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extern MMXRegister mm8;
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extern MMXRegister mm9;
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extern MMXRegister mm10;
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extern MMXRegister mm11;
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extern MMXRegister mm12;
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extern MMXRegister mm13;
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extern MMXRegister mm14;
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extern MMXRegister mm15;
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2009-05-06 12:08:50 +00:00
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struct XMMRegister {
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2009-06-23 11:26:05 +00:00
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bool is_valid() const { return 0 <= code_ && code_ < 16; }
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2009-05-06 12:08:50 +00:00
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int code() const {
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ASSERT(is_valid());
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return code_;
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}
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2009-07-03 13:30:15 +00:00
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// Return the high bit of the register code as a 0 or 1. Used often
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// when constructing the REX prefix byte.
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int high_bit() const {
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return code_ >> 3;
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}
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// Return the 3 low bits of the register code. Used when encoding registers
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// in modR/M, SIB, and opcode bytes.
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int low_bits() const {
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return code_ & 0x7;
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}
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2009-05-06 12:08:50 +00:00
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int code_;
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};
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extern XMMRegister xmm0;
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extern XMMRegister xmm1;
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extern XMMRegister xmm2;
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extern XMMRegister xmm3;
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extern XMMRegister xmm4;
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extern XMMRegister xmm5;
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extern XMMRegister xmm6;
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extern XMMRegister xmm7;
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2009-05-26 07:58:36 +00:00
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extern XMMRegister xmm8;
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extern XMMRegister xmm9;
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extern XMMRegister xmm10;
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extern XMMRegister xmm11;
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extern XMMRegister xmm12;
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extern XMMRegister xmm13;
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extern XMMRegister xmm14;
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extern XMMRegister xmm15;
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2009-05-06 12:08:50 +00:00
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2009-05-05 14:39:05 +00:00
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enum Condition {
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// any value < 0 is considered no_condition
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no_condition = -1,
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overflow = 0,
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no_overflow = 1,
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below = 2,
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above_equal = 3,
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equal = 4,
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not_equal = 5,
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below_equal = 6,
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above = 7,
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negative = 8,
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positive = 9,
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parity_even = 10,
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parity_odd = 11,
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less = 12,
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greater_equal = 13,
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less_equal = 14,
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greater = 15,
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2009-10-08 12:36:12 +00:00
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// Fake conditions that are handled by the
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// opcodes using them.
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always = 16,
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never = 17,
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2009-05-05 14:39:05 +00:00
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// aliases
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carry = below,
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not_carry = above_equal,
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zero = equal,
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not_zero = not_equal,
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sign = negative,
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2009-10-08 12:36:12 +00:00
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not_sign = positive,
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last_condition = greater
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2009-05-05 14:39:05 +00:00
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};
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2009-05-06 12:08:50 +00:00
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// Returns the equivalent of !cc.
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// Negation of the default no_condition (-1) results in a non-default
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// no_condition value (-2). As long as tests for no_condition check
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// for condition < 0, this will work as expected.
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inline Condition NegateCondition(Condition cc);
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// Corresponds to transposing the operands of a comparison.
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inline Condition ReverseCondition(Condition cc) {
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switch (cc) {
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case below:
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return above;
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case above:
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return below;
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case above_equal:
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return below_equal;
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case below_equal:
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return above_equal;
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case less:
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return greater;
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case greater:
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return less;
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case greater_equal:
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return less_equal;
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case less_equal:
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return greater_equal;
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default:
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return cc;
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};
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}
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2009-05-05 14:39:05 +00:00
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enum Hint {
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no_hint = 0,
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not_taken = 0x2e,
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taken = 0x3e
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};
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2009-05-06 12:08:50 +00:00
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// The result of negating a hint is as if the corresponding condition
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// were negated by NegateCondition. That is, no_hint is mapped to
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// itself and not_taken and taken are mapped to each other.
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inline Hint NegateHint(Hint hint) {
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return (hint == no_hint)
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? no_hint
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: ((hint == not_taken) ? taken : not_taken);
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}
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// -----------------------------------------------------------------------------
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// Machine instruction Immediates
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class Immediate BASE_EMBEDDED {
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public:
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2009-05-28 09:18:17 +00:00
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explicit Immediate(int32_t value) : value_(value) {}
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2009-05-06 12:08:50 +00:00
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private:
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2009-05-28 09:18:17 +00:00
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int32_t value_;
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2009-05-06 12:08:50 +00:00
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friend class Assembler;
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};
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// -----------------------------------------------------------------------------
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// Machine instruction Operands
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enum ScaleFactor {
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2009-06-24 08:28:42 +00:00
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times_1 = 0,
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times_2 = 1,
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times_4 = 2,
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times_8 = 3,
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times_int_size = times_4,
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2009-07-30 09:18:14 +00:00
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times_half_pointer_size = times_4,
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2009-06-24 08:28:42 +00:00
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times_pointer_size = times_8
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2009-05-06 12:08:50 +00:00
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};
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class Operand BASE_EMBEDDED {
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public:
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// [base + disp/r]
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2009-06-10 09:48:15 +00:00
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Operand(Register base, int32_t disp);
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2009-05-06 12:08:50 +00:00
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// [base + index*scale + disp/r]
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2009-05-27 08:15:31 +00:00
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Operand(Register base,
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Register index,
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ScaleFactor scale,
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int32_t disp);
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2009-05-06 12:08:50 +00:00
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// [index*scale + disp/r]
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2009-05-27 08:15:31 +00:00
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Operand(Register index,
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ScaleFactor scale,
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int32_t disp);
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2009-05-06 12:08:50 +00:00
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private:
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byte rex_;
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byte buf_[10];
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// The number of bytes in buf_.
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unsigned int len_;
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RelocInfo::Mode rmode_;
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2009-06-03 13:30:31 +00:00
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// Set the ModR/M byte without an encoded 'reg' register. The
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2009-05-06 12:08:50 +00:00
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// register is encoded later as part of the emit_operand operation.
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2009-05-27 08:15:31 +00:00
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// set_modrm can be called before or after set_sib and set_disp*.
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2009-05-06 12:08:50 +00:00
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inline void set_modrm(int mod, Register rm);
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2009-05-27 08:15:31 +00:00
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// Set the SIB byte if one is needed. Sets the length to 2 rather than 1.
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2009-05-06 12:08:50 +00:00
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inline void set_sib(ScaleFactor scale, Register index, Register base);
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2009-05-27 08:15:31 +00:00
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// Adds operand displacement fields (offsets added to the memory address).
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// Needs to be called after set_sib, not before it.
|
|
|
|
inline void set_disp8(int disp);
|
|
|
|
inline void set_disp32(int disp);
|
2009-05-06 12:08:50 +00:00
|
|
|
|
2009-05-27 08:15:31 +00:00
|
|
|
friend class Assembler;
|
2009-05-06 12:08:50 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
// CpuFeatures keeps track of which features are supported by the target CPU.
|
|
|
|
// Supported features must be enabled by a Scope before use.
|
|
|
|
// Example:
|
2009-06-23 11:26:05 +00:00
|
|
|
// if (CpuFeatures::IsSupported(SSE3)) {
|
|
|
|
// CpuFeatures::Scope fscope(SSE3);
|
|
|
|
// // Generate SSE3 floating point code.
|
2009-05-06 12:08:50 +00:00
|
|
|
// } else {
|
2009-06-23 11:26:05 +00:00
|
|
|
// // Generate standard x87 or SSE2 floating point code.
|
2009-05-06 12:08:50 +00:00
|
|
|
// }
|
|
|
|
class CpuFeatures : public AllStatic {
|
|
|
|
public:
|
|
|
|
// Feature flags bit positions. They are mostly based on the CPUID spec.
|
|
|
|
// (We assign CPUID itself to one of the currently reserved bits --
|
|
|
|
// feel free to change this if needed.)
|
2009-09-01 11:32:20 +00:00
|
|
|
enum Feature { SSE3 = 32,
|
|
|
|
SSE2 = 26,
|
|
|
|
CMOV = 15,
|
|
|
|
RDTSC = 4,
|
|
|
|
CPUID = 10,
|
|
|
|
SAHF = 0};
|
2009-05-06 12:08:50 +00:00
|
|
|
// Detect features of the target CPU. Set safe defaults if the serializer
|
|
|
|
// is enabled (snapshots must be portable).
|
|
|
|
static void Probe();
|
|
|
|
// Check whether a feature is supported by the target CPU.
|
|
|
|
static bool IsSupported(Feature f) {
|
2009-10-08 14:27:46 +00:00
|
|
|
if (f == SSE2 && !FLAG_enable_sse2) return false;
|
|
|
|
if (f == SSE3 && !FLAG_enable_sse3) return false;
|
|
|
|
if (f == CMOV && !FLAG_enable_cmov) return false;
|
|
|
|
if (f == RDTSC && !FLAG_enable_rdtsc) return false;
|
|
|
|
if (f == SAHF && !FLAG_enable_sahf) return false;
|
2009-06-02 13:40:52 +00:00
|
|
|
return (supported_ & (V8_UINT64_C(1) << f)) != 0;
|
2009-05-06 12:08:50 +00:00
|
|
|
}
|
|
|
|
// Check whether a feature is currently enabled.
|
|
|
|
static bool IsEnabled(Feature f) {
|
2009-06-02 13:40:52 +00:00
|
|
|
return (enabled_ & (V8_UINT64_C(1) << f)) != 0;
|
2009-05-06 12:08:50 +00:00
|
|
|
}
|
|
|
|
// Enable a specified feature within a scope.
|
|
|
|
class Scope BASE_EMBEDDED {
|
|
|
|
#ifdef DEBUG
|
|
|
|
public:
|
|
|
|
explicit Scope(Feature f) {
|
|
|
|
ASSERT(CpuFeatures::IsSupported(f));
|
|
|
|
old_enabled_ = CpuFeatures::enabled_;
|
2009-06-02 13:40:52 +00:00
|
|
|
CpuFeatures::enabled_ |= (V8_UINT64_C(1) << f);
|
2009-05-06 12:08:50 +00:00
|
|
|
}
|
|
|
|
~Scope() { CpuFeatures::enabled_ = old_enabled_; }
|
|
|
|
private:
|
|
|
|
uint64_t old_enabled_;
|
|
|
|
#else
|
|
|
|
public:
|
|
|
|
explicit Scope(Feature f) {}
|
|
|
|
#endif
|
|
|
|
};
|
|
|
|
private:
|
2009-06-23 11:26:05 +00:00
|
|
|
// Safe defaults include SSE2 and CMOV for X64. It is always available, if
|
|
|
|
// anyone checks, but they shouldn't need to check.
|
|
|
|
static const uint64_t kDefaultCpuFeatures =
|
|
|
|
(1 << CpuFeatures::SSE2 | 1 << CpuFeatures::CMOV);
|
2009-05-06 12:08:50 +00:00
|
|
|
static uint64_t supported_;
|
|
|
|
static uint64_t enabled_;
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
class Assembler : public Malloced {
|
|
|
|
private:
|
2009-06-23 09:50:51 +00:00
|
|
|
// We check before assembling an instruction that there is sufficient
|
|
|
|
// space to write an instruction and its relocation information.
|
|
|
|
// The relocation writer's position must be kGap bytes above the end of
|
2009-05-06 12:08:50 +00:00
|
|
|
// the generated instructions. This leaves enough space for the
|
2009-06-23 09:50:51 +00:00
|
|
|
// longest possible x64 instruction, 15 bytes, and the longest possible
|
|
|
|
// relocation information encoding, RelocInfoWriter::kMaxLength == 16.
|
|
|
|
// (There is a 15 byte limit on x64 instruction length that rules out some
|
|
|
|
// otherwise valid instructions.)
|
|
|
|
// This allows for a single, fast space check per instruction.
|
2009-05-06 12:08:50 +00:00
|
|
|
static const int kGap = 32;
|
|
|
|
|
|
|
|
public:
|
|
|
|
// Create an assembler. Instructions and relocation information are emitted
|
|
|
|
// into a buffer, with the instructions starting from the beginning and the
|
|
|
|
// relocation information starting from the end of the buffer. See CodeDesc
|
|
|
|
// for a detailed comment on the layout (globals.h).
|
|
|
|
//
|
|
|
|
// If the provided buffer is NULL, the assembler allocates and grows its own
|
|
|
|
// buffer, and buffer_size determines the initial buffer size. The buffer is
|
|
|
|
// owned by the assembler and deallocated upon destruction of the assembler.
|
|
|
|
//
|
|
|
|
// If the provided buffer is not NULL, the assembler uses the provided buffer
|
|
|
|
// for code generation and assumes its size to be buffer_size. If the buffer
|
|
|
|
// is too small, a fatal error occurs. No deallocation of the buffer is done
|
|
|
|
// upon destruction of the assembler.
|
|
|
|
Assembler(void* buffer, int buffer_size);
|
|
|
|
~Assembler();
|
|
|
|
|
|
|
|
// GetCode emits any pending (non-emitted) code and fills the descriptor
|
|
|
|
// desc. GetCode() is idempotent; it returns the same result if no other
|
|
|
|
// Assembler functions are invoked in between GetCode() calls.
|
|
|
|
void GetCode(CodeDesc* desc);
|
|
|
|
|
2009-10-06 13:11:05 +00:00
|
|
|
// Read/Modify the code target in the relative branch/call instruction at pc.
|
|
|
|
// On the x64 architecture, we use relative jumps with a 32-bit displacement
|
|
|
|
// to jump to other Code objects in the Code space in the heap.
|
|
|
|
// Jumps to C functions are done indirectly through a 64-bit register holding
|
|
|
|
// the absolute address of the target.
|
|
|
|
// These functions convert between absolute Addresses of Code objects and
|
|
|
|
// the relative displacements stored in the code.
|
2009-06-02 13:40:52 +00:00
|
|
|
static inline Address target_address_at(Address pc);
|
|
|
|
static inline void set_target_address_at(Address pc, Address target);
|
2009-10-30 10:23:12 +00:00
|
|
|
|
2009-10-28 12:37:54 +00:00
|
|
|
// This sets the branch destination (which is in the instruction on x64).
|
2009-10-30 10:23:12 +00:00
|
|
|
// This is for calls and branches within generated code.
|
2009-10-28 12:37:54 +00:00
|
|
|
inline static void set_target_at(Address instruction_payload,
|
|
|
|
Address target) {
|
|
|
|
set_target_address_at(instruction_payload, target);
|
|
|
|
}
|
2009-10-30 10:23:12 +00:00
|
|
|
|
|
|
|
// This sets the branch destination (which is a load instruction on x64).
|
|
|
|
// This is for calls and branches to runtime code.
|
|
|
|
inline static void set_external_target_at(Address instruction_payload,
|
|
|
|
Address target) {
|
|
|
|
*reinterpret_cast<Address*>(instruction_payload) = target;
|
|
|
|
}
|
|
|
|
|
2009-10-06 13:11:05 +00:00
|
|
|
inline Handle<Object> code_target_object_handle_at(Address pc);
|
2009-10-27 11:54:01 +00:00
|
|
|
// Number of bytes taken up by the branch target in the code.
|
2009-10-30 10:23:12 +00:00
|
|
|
static const int kCallTargetSize = 4; // Use 32-bit displacement.
|
|
|
|
static const int kExternalTargetSize = 8; // Use 64-bit absolute.
|
2009-05-06 12:08:50 +00:00
|
|
|
// Distance between the address of the code target in the call instruction
|
2009-10-06 13:11:05 +00:00
|
|
|
// and the return address pushed on the stack.
|
|
|
|
static const int kCallTargetAddressOffset = 4; // Use 32-bit displacement.
|
|
|
|
// Distance between the start of the JS return sequence and where the
|
|
|
|
// 32-bit displacement of a near call would be, relative to the pushed
|
|
|
|
// return address. TODO: Use return sequence length instead.
|
|
|
|
// Should equal Debug::kX64JSReturnSequenceLength - kCallTargetAddressOffset;
|
|
|
|
static const int kPatchReturnSequenceAddressOffset = 13 - 4;
|
|
|
|
// TODO(X64): Rename this, removing the "Real", after changing the above.
|
|
|
|
static const int kRealPatchReturnSequenceAddressOffset = 2;
|
2009-05-06 12:08:50 +00:00
|
|
|
// ---------------------------------------------------------------------------
|
|
|
|
// Code generation
|
|
|
|
//
|
2009-05-25 14:00:30 +00:00
|
|
|
// Function names correspond one-to-one to x64 instruction mnemonics.
|
|
|
|
// Unless specified otherwise, instructions operate on 64-bit operands.
|
|
|
|
//
|
|
|
|
// If we need versions of an assembly instruction that operate on different
|
|
|
|
// width arguments, we add a single-letter suffix specifying the width.
|
2009-06-10 15:53:46 +00:00
|
|
|
// This is done for the following instructions: mov, cmp, inc, dec,
|
|
|
|
// add, sub, and test.
|
2009-05-25 14:00:30 +00:00
|
|
|
// There are no versions of these instructions without the suffix.
|
|
|
|
// - Instructions on 8-bit (byte) operands/registers have a trailing 'b'.
|
|
|
|
// - Instructions on 16-bit (word) operands/registers have a trailing 'w'.
|
|
|
|
// - Instructions on 32-bit (doubleword) operands/registers use 'l'.
|
|
|
|
// - Instructions on 64-bit (quadword) operands/registers use 'q'.
|
|
|
|
//
|
|
|
|
// Some mnemonics, such as "and", are the same as C++ keywords.
|
|
|
|
// Naming conflicts with C++ keywords are resolved by adding a trailing '_'.
|
2009-05-06 12:08:50 +00:00
|
|
|
|
|
|
|
// Insert the smallest number of nop instructions
|
|
|
|
// possible to align the pc offset to a multiple
|
|
|
|
// of m. m must be a power of 2.
|
|
|
|
void Align(int m);
|
|
|
|
|
|
|
|
// Stack
|
2009-06-02 13:40:52 +00:00
|
|
|
void pushfq();
|
|
|
|
void popfq();
|
2009-05-06 12:08:50 +00:00
|
|
|
|
2009-06-02 13:40:52 +00:00
|
|
|
void push(Immediate value);
|
2009-05-06 12:08:50 +00:00
|
|
|
void push(Register src);
|
|
|
|
void push(const Operand& src);
|
|
|
|
void push(Label* label, RelocInfo::Mode relocation_mode);
|
|
|
|
|
|
|
|
void pop(Register dst);
|
|
|
|
void pop(const Operand& dst);
|
|
|
|
|
2009-06-02 13:40:52 +00:00
|
|
|
void enter(Immediate size);
|
2009-05-06 12:08:50 +00:00
|
|
|
void leave();
|
|
|
|
|
|
|
|
// Moves
|
2009-05-28 09:18:17 +00:00
|
|
|
void movb(Register dst, const Operand& src);
|
2009-06-03 13:30:31 +00:00
|
|
|
void movb(Register dst, Immediate imm);
|
2009-05-28 09:18:17 +00:00
|
|
|
void movb(const Operand& dst, Register src);
|
|
|
|
|
2009-10-20 15:26:17 +00:00
|
|
|
// Move the low 16 bits of a 64-bit register value to a 16-bit
|
|
|
|
// memory location.
|
|
|
|
void movw(const Operand& dst, Register src);
|
|
|
|
|
2009-06-02 13:40:52 +00:00
|
|
|
void movl(Register dst, Register src);
|
|
|
|
void movl(Register dst, const Operand& src);
|
|
|
|
void movl(const Operand& dst, Register src);
|
2009-06-10 15:53:46 +00:00
|
|
|
void movl(const Operand& dst, Immediate imm);
|
2009-06-03 10:30:50 +00:00
|
|
|
// Load a 32-bit immediate value, zero-extended to 64 bits.
|
|
|
|
void movl(Register dst, Immediate imm32);
|
2009-06-02 13:40:52 +00:00
|
|
|
|
2009-08-14 11:24:32 +00:00
|
|
|
// Move 64 bit register value to 64-bit memory location.
|
|
|
|
void movq(const Operand& dst, Register src);
|
|
|
|
// Move 64 bit memory location to 64-bit register value.
|
2009-05-28 09:18:17 +00:00
|
|
|
void movq(Register dst, const Operand& src);
|
2009-08-14 11:24:32 +00:00
|
|
|
void movq(Register dst, Register src);
|
2009-06-03 10:30:50 +00:00
|
|
|
// Sign extends immediate 32-bit value to 64 bits.
|
|
|
|
void movq(Register dst, Immediate x);
|
2009-08-14 11:24:32 +00:00
|
|
|
// Move the offset of the label location relative to the current
|
|
|
|
// position (after the move) to the destination.
|
|
|
|
void movl(const Operand& dst, Label* src);
|
2009-06-03 10:30:50 +00:00
|
|
|
|
2009-06-10 09:48:15 +00:00
|
|
|
// Move sign extended immediate to memory location.
|
|
|
|
void movq(const Operand& dst, Immediate value);
|
2009-05-28 09:18:17 +00:00
|
|
|
// New x64 instructions to load a 64-bit immediate into a register.
|
|
|
|
// All 64-bit immediates must have a relocation mode.
|
|
|
|
void movq(Register dst, void* ptr, RelocInfo::Mode rmode);
|
|
|
|
void movq(Register dst, int64_t value, RelocInfo::Mode rmode);
|
|
|
|
void movq(Register dst, const char* s, RelocInfo::Mode rmode);
|
2009-06-04 11:54:14 +00:00
|
|
|
// Moves the address of the external reference into the register.
|
|
|
|
void movq(Register dst, ExternalReference ext);
|
2009-05-28 09:18:17 +00:00
|
|
|
void movq(Register dst, Handle<Object> handle, RelocInfo::Mode rmode);
|
|
|
|
|
2009-10-20 15:26:17 +00:00
|
|
|
void movsxbq(Register dst, const Operand& src);
|
|
|
|
void movsxwq(Register dst, const Operand& src);
|
2009-06-17 11:50:33 +00:00
|
|
|
void movsxlq(Register dst, Register src);
|
2009-06-24 13:48:09 +00:00
|
|
|
void movsxlq(Register dst, const Operand& src);
|
2009-06-17 11:50:33 +00:00
|
|
|
void movzxbq(Register dst, const Operand& src);
|
2009-08-07 11:16:26 +00:00
|
|
|
void movzxbl(Register dst, const Operand& src);
|
2009-10-20 15:26:17 +00:00
|
|
|
void movzxwq(Register dst, const Operand& src);
|
2009-08-07 11:16:26 +00:00
|
|
|
void movzxwl(Register dst, const Operand& src);
|
2009-06-17 11:50:33 +00:00
|
|
|
|
2009-05-28 09:18:17 +00:00
|
|
|
// New x64 instruction to load from an immediate 64-bit pointer into RAX.
|
|
|
|
void load_rax(void* ptr, RelocInfo::Mode rmode);
|
2009-06-04 11:54:14 +00:00
|
|
|
void load_rax(ExternalReference ext);
|
2009-05-06 12:08:50 +00:00
|
|
|
|
2009-06-23 11:26:05 +00:00
|
|
|
// Conditional moves.
|
|
|
|
void cmovq(Condition cc, Register dst, Register src);
|
|
|
|
void cmovq(Condition cc, Register dst, const Operand& src);
|
|
|
|
void cmovl(Condition cc, Register dst, Register src);
|
|
|
|
void cmovl(Condition cc, Register dst, const Operand& src);
|
2009-05-06 12:08:50 +00:00
|
|
|
|
|
|
|
// Exchange two registers
|
|
|
|
void xchg(Register dst, Register src);
|
|
|
|
|
|
|
|
// Arithmetics
|
2009-06-17 11:50:33 +00:00
|
|
|
void addl(Register dst, Register src) {
|
2009-08-14 11:24:32 +00:00
|
|
|
if (dst.low_bits() == 4) { // Forces SIB byte.
|
|
|
|
arithmetic_op_32(0x01, src, dst);
|
|
|
|
} else {
|
|
|
|
arithmetic_op_32(0x03, dst, src);
|
|
|
|
}
|
2009-06-17 11:50:33 +00:00
|
|
|
}
|
|
|
|
|
2009-06-23 11:26:05 +00:00
|
|
|
void addl(Register dst, Immediate src) {
|
|
|
|
immediate_arithmetic_op_32(0x0, dst, src);
|
|
|
|
}
|
|
|
|
|
2009-07-21 13:30:46 +00:00
|
|
|
void addl(Register dst, const Operand& src) {
|
|
|
|
arithmetic_op_32(0x03, dst, src);
|
|
|
|
}
|
|
|
|
|
2009-07-03 09:24:53 +00:00
|
|
|
void addl(const Operand& dst, Immediate src) {
|
|
|
|
immediate_arithmetic_op_32(0x0, dst, src);
|
|
|
|
}
|
|
|
|
|
2009-07-21 13:30:46 +00:00
|
|
|
void addq(Register dst, Register src) {
|
2009-05-28 09:18:17 +00:00
|
|
|
arithmetic_op(0x03, dst, src);
|
|
|
|
}
|
|
|
|
|
2009-07-21 13:30:46 +00:00
|
|
|
void addq(Register dst, const Operand& src) {
|
|
|
|
arithmetic_op(0x03, dst, src);
|
|
|
|
}
|
2009-05-28 10:06:48 +00:00
|
|
|
|
2009-06-10 15:53:46 +00:00
|
|
|
void addq(const Operand& dst, Register src) {
|
2009-05-28 09:18:17 +00:00
|
|
|
arithmetic_op(0x01, src, dst);
|
|
|
|
}
|
|
|
|
|
2009-06-10 15:53:46 +00:00
|
|
|
void addq(Register dst, Immediate src) {
|
2009-05-28 09:18:17 +00:00
|
|
|
immediate_arithmetic_op(0x0, dst, src);
|
|
|
|
}
|
|
|
|
|
2009-06-10 15:53:46 +00:00
|
|
|
void addq(const Operand& dst, Immediate src) {
|
2009-05-28 09:18:17 +00:00
|
|
|
immediate_arithmetic_op(0x0, dst, src);
|
|
|
|
}
|
|
|
|
|
2009-06-24 13:46:07 +00:00
|
|
|
void cmpb(Register dst, Immediate src) {
|
|
|
|
immediate_arithmetic_op_8(0x7, dst, src);
|
|
|
|
}
|
|
|
|
|
2009-08-14 11:24:32 +00:00
|
|
|
void cmpb_al(Immediate src);
|
|
|
|
|
|
|
|
void cmpb(Register dst, Register src) {
|
|
|
|
arithmetic_op(0x3A, dst, src);
|
|
|
|
}
|
|
|
|
|
|
|
|
void cmpb(Register dst, const Operand& src) {
|
|
|
|
arithmetic_op(0x3A, dst, src);
|
|
|
|
}
|
|
|
|
|
|
|
|
void cmpb(const Operand& dst, Register src) {
|
|
|
|
arithmetic_op(0x38, src, dst);
|
|
|
|
}
|
|
|
|
|
2009-06-11 13:51:46 +00:00
|
|
|
void cmpb(const Operand& dst, Immediate src) {
|
|
|
|
immediate_arithmetic_op_8(0x7, dst, src);
|
|
|
|
}
|
|
|
|
|
2009-08-14 11:24:32 +00:00
|
|
|
void cmpw(const Operand& dst, Immediate src) {
|
|
|
|
immediate_arithmetic_op_16(0x7, dst, src);
|
|
|
|
}
|
|
|
|
|
|
|
|
void cmpw(Register dst, Immediate src) {
|
|
|
|
immediate_arithmetic_op_16(0x7, dst, src);
|
|
|
|
}
|
|
|
|
|
|
|
|
void cmpw(Register dst, const Operand& src) {
|
|
|
|
arithmetic_op_16(0x3B, dst, src);
|
|
|
|
}
|
|
|
|
|
|
|
|
void cmpw(Register dst, Register src) {
|
|
|
|
arithmetic_op_16(0x3B, dst, src);
|
|
|
|
}
|
|
|
|
|
|
|
|
void cmpw(const Operand& dst, Register src) {
|
|
|
|
arithmetic_op_16(0x39, src, dst);
|
|
|
|
}
|
|
|
|
|
2009-07-06 13:21:39 +00:00
|
|
|
void cmpl(Register dst, Register src) {
|
|
|
|
arithmetic_op_32(0x3B, dst, src);
|
|
|
|
}
|
|
|
|
|
2009-07-07 12:40:15 +00:00
|
|
|
void cmpl(Register dst, const Operand& src) {
|
2009-07-21 13:30:46 +00:00
|
|
|
arithmetic_op_32(0x3B, dst, src);
|
2009-07-07 12:40:15 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void cmpl(const Operand& dst, Register src) {
|
2009-07-21 13:30:46 +00:00
|
|
|
arithmetic_op_32(0x39, src, dst);
|
2009-07-07 12:40:15 +00:00
|
|
|
}
|
|
|
|
|
2009-07-06 13:21:39 +00:00
|
|
|
void cmpl(Register dst, Immediate src) {
|
|
|
|
immediate_arithmetic_op_32(0x7, dst, src);
|
|
|
|
}
|
|
|
|
|
2009-07-07 12:40:15 +00:00
|
|
|
void cmpl(const Operand& dst, Immediate src) {
|
|
|
|
immediate_arithmetic_op_32(0x7, dst, src);
|
|
|
|
}
|
|
|
|
|
2009-06-10 15:53:46 +00:00
|
|
|
void cmpq(Register dst, Register src) {
|
2009-05-28 09:18:17 +00:00
|
|
|
arithmetic_op(0x3B, dst, src);
|
|
|
|
}
|
|
|
|
|
2009-06-10 15:53:46 +00:00
|
|
|
void cmpq(Register dst, const Operand& src) {
|
2009-05-28 09:18:17 +00:00
|
|
|
arithmetic_op(0x3B, dst, src);
|
|
|
|
}
|
|
|
|
|
2009-06-10 15:53:46 +00:00
|
|
|
void cmpq(const Operand& dst, Register src) {
|
2009-05-28 09:18:17 +00:00
|
|
|
arithmetic_op(0x39, src, dst);
|
|
|
|
}
|
|
|
|
|
2009-06-10 15:53:46 +00:00
|
|
|
void cmpq(Register dst, Immediate src) {
|
2009-05-28 09:18:17 +00:00
|
|
|
immediate_arithmetic_op(0x7, dst, src);
|
|
|
|
}
|
|
|
|
|
2009-06-10 15:53:46 +00:00
|
|
|
void cmpq(const Operand& dst, Immediate src) {
|
2009-05-28 09:18:17 +00:00
|
|
|
immediate_arithmetic_op(0x7, dst, src);
|
|
|
|
}
|
2009-05-06 12:08:50 +00:00
|
|
|
|
2009-05-28 10:06:48 +00:00
|
|
|
void and_(Register dst, Register src) {
|
|
|
|
arithmetic_op(0x23, dst, src);
|
|
|
|
}
|
|
|
|
|
|
|
|
void and_(Register dst, const Operand& src) {
|
|
|
|
arithmetic_op(0x23, dst, src);
|
|
|
|
}
|
|
|
|
|
|
|
|
void and_(const Operand& dst, Register src) {
|
|
|
|
arithmetic_op(0x21, src, dst);
|
|
|
|
}
|
|
|
|
|
|
|
|
void and_(Register dst, Immediate src) {
|
|
|
|
immediate_arithmetic_op(0x4, dst, src);
|
|
|
|
}
|
2009-05-06 12:08:50 +00:00
|
|
|
|
2009-05-28 10:06:48 +00:00
|
|
|
void and_(const Operand& dst, Immediate src) {
|
|
|
|
immediate_arithmetic_op(0x4, dst, src);
|
|
|
|
}
|
2009-05-06 12:08:50 +00:00
|
|
|
|
2009-09-23 13:04:07 +00:00
|
|
|
void andl(Register dst, Immediate src) {
|
|
|
|
immediate_arithmetic_op_32(0x4, dst, src);
|
|
|
|
}
|
|
|
|
|
2009-10-08 12:36:12 +00:00
|
|
|
void andl(Register dst, Register src) {
|
|
|
|
arithmetic_op_32(0x23, dst, src);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2009-06-10 15:53:46 +00:00
|
|
|
void decq(Register dst);
|
|
|
|
void decq(const Operand& dst);
|
2009-07-24 11:22:35 +00:00
|
|
|
void decl(Register dst);
|
2009-06-10 15:53:46 +00:00
|
|
|
void decl(const Operand& dst);
|
2009-10-08 07:09:46 +00:00
|
|
|
void decb(Register dst);
|
|
|
|
void decb(const Operand& dst);
|
2009-05-06 12:08:50 +00:00
|
|
|
|
2009-06-02 13:40:52 +00:00
|
|
|
// Sign-extends rax into rdx:rax.
|
|
|
|
void cqo();
|
2009-07-30 07:31:54 +00:00
|
|
|
// Sign-extends eax into edx:eax.
|
|
|
|
void cdq();
|
2009-05-06 12:08:50 +00:00
|
|
|
|
2009-06-03 13:30:31 +00:00
|
|
|
// Divide rdx:rax by src. Quotient in rax, remainder in rdx.
|
2009-07-30 07:31:54 +00:00
|
|
|
void idivq(Register src);
|
|
|
|
// Divide edx:eax by lower 32 bits of src. Quotient in eax, rem. in edx.
|
|
|
|
void idivl(Register src);
|
2009-05-06 12:08:50 +00:00
|
|
|
|
2009-06-29 09:32:06 +00:00
|
|
|
// Signed multiply instructions.
|
|
|
|
void imul(Register src); // rdx:rax = rax * src.
|
|
|
|
void imul(Register dst, Register src); // dst = dst * src.
|
|
|
|
void imul(Register dst, const Operand& src); // dst = dst * src.
|
|
|
|
void imul(Register dst, Register src, Immediate imm); // dst = src * imm.
|
2009-06-17 11:50:33 +00:00
|
|
|
// Multiply 32 bit registers
|
2009-06-29 09:32:06 +00:00
|
|
|
void imull(Register dst, Register src); // dst = dst * src.
|
2009-05-06 12:08:50 +00:00
|
|
|
|
2009-06-10 15:53:46 +00:00
|
|
|
void incq(Register dst);
|
|
|
|
void incq(const Operand& dst);
|
|
|
|
void incl(const Operand& dst);
|
2009-05-06 12:08:50 +00:00
|
|
|
|
|
|
|
void lea(Register dst, const Operand& src);
|
|
|
|
|
2009-06-03 13:30:31 +00:00
|
|
|
// Multiply rax by src, put the result in rdx:rax.
|
2009-05-06 12:08:50 +00:00
|
|
|
void mul(Register src);
|
|
|
|
|
|
|
|
void neg(Register dst);
|
2009-05-29 08:56:31 +00:00
|
|
|
void neg(const Operand& dst);
|
2009-09-10 12:55:27 +00:00
|
|
|
void negl(Register dst);
|
2009-05-06 12:08:50 +00:00
|
|
|
|
|
|
|
void not_(Register dst);
|
2009-05-29 08:56:31 +00:00
|
|
|
void not_(const Operand& dst);
|
2009-05-06 12:08:50 +00:00
|
|
|
|
2009-05-28 10:06:48 +00:00
|
|
|
void or_(Register dst, Register src) {
|
|
|
|
arithmetic_op(0x0B, dst, src);
|
|
|
|
}
|
|
|
|
|
2009-09-10 12:55:27 +00:00
|
|
|
void orl(Register dst, Register src) {
|
|
|
|
arithmetic_op_32(0x0B, dst, src);
|
|
|
|
}
|
|
|
|
|
2009-05-28 10:06:48 +00:00
|
|
|
void or_(Register dst, const Operand& src) {
|
|
|
|
arithmetic_op(0x0B, dst, src);
|
|
|
|
}
|
|
|
|
|
|
|
|
void or_(const Operand& dst, Register src) {
|
|
|
|
arithmetic_op(0x09, src, dst);
|
|
|
|
}
|
|
|
|
|
|
|
|
void or_(Register dst, Immediate src) {
|
|
|
|
immediate_arithmetic_op(0x1, dst, src);
|
|
|
|
}
|
|
|
|
|
2009-10-08 12:36:12 +00:00
|
|
|
void orl(Register dst, Immediate src) {
|
|
|
|
immediate_arithmetic_op_32(0x1, dst, src);
|
|
|
|
}
|
|
|
|
|
2009-05-28 10:06:48 +00:00
|
|
|
void or_(const Operand& dst, Immediate src) {
|
|
|
|
immediate_arithmetic_op(0x1, dst, src);
|
|
|
|
}
|
|
|
|
|
2009-10-08 12:36:12 +00:00
|
|
|
void orl(const Operand& dst, Immediate src) {
|
|
|
|
immediate_arithmetic_op_32(0x1, dst, src);
|
|
|
|
}
|
|
|
|
|
2009-05-06 12:08:50 +00:00
|
|
|
|
2009-10-08 12:36:12 +00:00
|
|
|
void rcl(Register dst, Immediate imm8) {
|
|
|
|
shift(dst, imm8, 0x2);
|
|
|
|
}
|
|
|
|
|
|
|
|
void rol(Register dst, Immediate imm8) {
|
|
|
|
shift(dst, imm8, 0x0);
|
|
|
|
}
|
|
|
|
|
|
|
|
void rcr(Register dst, Immediate imm8) {
|
|
|
|
shift(dst, imm8, 0x3);
|
|
|
|
}
|
|
|
|
|
|
|
|
void ror(Register dst, Immediate imm8) {
|
|
|
|
shift(dst, imm8, 0x1);
|
|
|
|
}
|
2009-05-06 12:08:50 +00:00
|
|
|
|
2009-06-03 13:30:31 +00:00
|
|
|
// Shifts dst:src left by cl bits, affecting only dst.
|
|
|
|
void shld(Register dst, Register src);
|
2009-05-06 12:08:50 +00:00
|
|
|
|
2009-06-03 13:30:31 +00:00
|
|
|
// Shifts src:dst right by cl bits, affecting only dst.
|
|
|
|
void shrd(Register dst, Register src);
|
2009-05-06 12:08:50 +00:00
|
|
|
|
2009-06-02 11:43:26 +00:00
|
|
|
// Shifts dst right, duplicating sign bit, by shift_amount bits.
|
|
|
|
// Shifting by 1 is handled efficiently.
|
|
|
|
void sar(Register dst, Immediate shift_amount) {
|
|
|
|
shift(dst, shift_amount, 0x7);
|
|
|
|
}
|
|
|
|
|
2009-07-09 08:00:12 +00:00
|
|
|
// Shifts dst right, duplicating sign bit, by shift_amount bits.
|
|
|
|
// Shifting by 1 is handled efficiently.
|
|
|
|
void sarl(Register dst, Immediate shift_amount) {
|
|
|
|
shift_32(dst, shift_amount, 0x7);
|
|
|
|
}
|
|
|
|
|
2009-06-02 11:43:26 +00:00
|
|
|
// Shifts dst right, duplicating sign bit, by cl % 64 bits.
|
|
|
|
void sar(Register dst) {
|
|
|
|
shift(dst, 0x7);
|
|
|
|
}
|
|
|
|
|
2009-07-09 08:00:12 +00:00
|
|
|
// Shifts dst right, duplicating sign bit, by cl % 64 bits.
|
|
|
|
void sarl(Register dst) {
|
|
|
|
shift_32(dst, 0x7);
|
|
|
|
}
|
|
|
|
|
2009-06-02 11:43:26 +00:00
|
|
|
void shl(Register dst, Immediate shift_amount) {
|
|
|
|
shift(dst, shift_amount, 0x4);
|
|
|
|
}
|
|
|
|
|
|
|
|
void shl(Register dst) {
|
|
|
|
shift(dst, 0x4);
|
|
|
|
}
|
|
|
|
|
2009-06-17 11:50:33 +00:00
|
|
|
void shll(Register dst) {
|
|
|
|
shift_32(dst, 0x4);
|
|
|
|
}
|
|
|
|
|
2009-07-14 11:39:45 +00:00
|
|
|
void shll(Register dst, Immediate shift_amount) {
|
|
|
|
shift_32(dst, shift_amount, 0x4);
|
|
|
|
}
|
|
|
|
|
2009-06-02 11:43:26 +00:00
|
|
|
void shr(Register dst, Immediate shift_amount) {
|
|
|
|
shift(dst, shift_amount, 0x5);
|
|
|
|
}
|
|
|
|
|
|
|
|
void shr(Register dst) {
|
|
|
|
shift(dst, 0x5);
|
|
|
|
}
|
2009-05-06 12:08:50 +00:00
|
|
|
|
2009-06-17 11:50:33 +00:00
|
|
|
void shrl(Register dst) {
|
|
|
|
shift_32(dst, 0x5);
|
|
|
|
}
|
|
|
|
|
2009-07-24 11:22:35 +00:00
|
|
|
void shrl(Register dst, Immediate shift_amount) {
|
|
|
|
shift_32(dst, shift_amount, 0x5);
|
|
|
|
}
|
|
|
|
|
2009-06-04 11:54:14 +00:00
|
|
|
void store_rax(void* dst, RelocInfo::Mode mode);
|
|
|
|
void store_rax(ExternalReference ref);
|
|
|
|
|
2009-06-10 15:53:46 +00:00
|
|
|
void subq(Register dst, Register src) {
|
2009-05-28 10:06:48 +00:00
|
|
|
arithmetic_op(0x2B, dst, src);
|
|
|
|
}
|
|
|
|
|
2009-06-10 15:53:46 +00:00
|
|
|
void subq(Register dst, const Operand& src) {
|
2009-05-28 10:06:48 +00:00
|
|
|
arithmetic_op(0x2B, dst, src);
|
|
|
|
}
|
|
|
|
|
2009-06-10 15:53:46 +00:00
|
|
|
void subq(const Operand& dst, Register src) {
|
2009-05-28 10:06:48 +00:00
|
|
|
arithmetic_op(0x29, src, dst);
|
|
|
|
}
|
|
|
|
|
2009-06-10 15:53:46 +00:00
|
|
|
void subq(Register dst, Immediate src) {
|
2009-05-28 10:06:48 +00:00
|
|
|
immediate_arithmetic_op(0x5, dst, src);
|
|
|
|
}
|
|
|
|
|
2009-06-10 15:53:46 +00:00
|
|
|
void subq(const Operand& dst, Immediate src) {
|
2009-05-28 10:06:48 +00:00
|
|
|
immediate_arithmetic_op(0x5, dst, src);
|
|
|
|
}
|
|
|
|
|
2009-06-17 11:50:33 +00:00
|
|
|
void subl(Register dst, Register src) {
|
|
|
|
arithmetic_op_32(0x2B, dst, src);
|
|
|
|
}
|
|
|
|
|
2009-06-10 15:53:46 +00:00
|
|
|
void subl(const Operand& dst, Immediate src) {
|
|
|
|
immediate_arithmetic_op_32(0x5, dst, src);
|
|
|
|
}
|
|
|
|
|
2009-07-03 09:24:53 +00:00
|
|
|
void subl(Register dst, Immediate src) {
|
|
|
|
immediate_arithmetic_op_32(0x5, dst, src);
|
|
|
|
}
|
|
|
|
|
2009-08-14 11:24:32 +00:00
|
|
|
void subb(Register dst, Immediate src) {
|
|
|
|
immediate_arithmetic_op_8(0x5, dst, src);
|
|
|
|
}
|
|
|
|
|
2009-10-08 12:36:12 +00:00
|
|
|
void testb(Register dst, Register src);
|
2009-05-29 08:56:31 +00:00
|
|
|
void testb(Register reg, Immediate mask);
|
|
|
|
void testb(const Operand& op, Immediate mask);
|
2009-07-06 13:21:39 +00:00
|
|
|
void testl(Register dst, Register src);
|
2009-05-29 08:56:31 +00:00
|
|
|
void testl(Register reg, Immediate mask);
|
|
|
|
void testl(const Operand& op, Immediate mask);
|
2009-06-03 13:30:31 +00:00
|
|
|
void testq(const Operand& op, Register reg);
|
|
|
|
void testq(Register dst, Register src);
|
2009-06-10 09:48:15 +00:00
|
|
|
void testq(Register dst, Immediate mask);
|
2009-05-06 12:08:50 +00:00
|
|
|
|
2009-05-28 10:06:48 +00:00
|
|
|
void xor_(Register dst, Register src) {
|
2009-10-26 14:38:22 +00:00
|
|
|
if (dst.code() == src.code()) {
|
|
|
|
arithmetic_op_32(0x33, dst, src);
|
|
|
|
} else {
|
|
|
|
arithmetic_op(0x33, dst, src);
|
|
|
|
}
|
2009-05-28 10:06:48 +00:00
|
|
|
}
|
|
|
|
|
2009-09-10 12:55:27 +00:00
|
|
|
void xorl(Register dst, Register src) {
|
|
|
|
arithmetic_op_32(0x33, dst, src);
|
|
|
|
}
|
|
|
|
|
2009-05-28 10:06:48 +00:00
|
|
|
void xor_(Register dst, const Operand& src) {
|
|
|
|
arithmetic_op(0x33, dst, src);
|
|
|
|
}
|
|
|
|
|
|
|
|
void xor_(const Operand& dst, Register src) {
|
|
|
|
arithmetic_op(0x31, src, dst);
|
|
|
|
}
|
|
|
|
|
|
|
|
void xor_(Register dst, Immediate src) {
|
|
|
|
immediate_arithmetic_op(0x6, dst, src);
|
|
|
|
}
|
|
|
|
|
|
|
|
void xor_(const Operand& dst, Immediate src) {
|
|
|
|
immediate_arithmetic_op(0x6, dst, src);
|
|
|
|
}
|
|
|
|
|
2009-05-06 12:08:50 +00:00
|
|
|
// Bit operations.
|
|
|
|
void bt(const Operand& dst, Register src);
|
|
|
|
void bts(const Operand& dst, Register src);
|
|
|
|
|
|
|
|
// Miscellaneous
|
2009-10-08 12:36:12 +00:00
|
|
|
void clc();
|
2009-06-10 15:53:46 +00:00
|
|
|
void cpuid();
|
2009-05-06 12:08:50 +00:00
|
|
|
void hlt();
|
|
|
|
void int3();
|
|
|
|
void nop();
|
2009-06-02 07:21:05 +00:00
|
|
|
void nop(int n);
|
2009-05-06 12:08:50 +00:00
|
|
|
void rdtsc();
|
|
|
|
void ret(int imm16);
|
2009-06-10 15:53:46 +00:00
|
|
|
void setcc(Condition cc, Register reg);
|
2009-05-06 12:08:50 +00:00
|
|
|
|
|
|
|
// Label operations & relative jumps (PPUM Appendix D)
|
|
|
|
//
|
|
|
|
// Takes a branch opcode (cc) and a label (L) and generates
|
|
|
|
// either a backward branch or a forward branch and links it
|
|
|
|
// to the label fixup chain. Usage:
|
|
|
|
//
|
|
|
|
// Label L; // unbound label
|
|
|
|
// j(cc, &L); // forward branch to unbound label
|
|
|
|
// bind(&L); // bind label to the current pc
|
|
|
|
// j(cc, &L); // backward branch to bound label
|
|
|
|
// bind(&L); // illegal: a label may be bound only once
|
|
|
|
//
|
|
|
|
// Note: The same Label can be used for forward and backward branches
|
|
|
|
// but it may be bound only once.
|
|
|
|
|
|
|
|
void bind(Label* L); // binds an unbound label L to the current code position
|
|
|
|
|
|
|
|
// Calls
|
2009-06-02 07:21:05 +00:00
|
|
|
// Call near relative 32-bit displacement, relative to next instruction.
|
2009-05-06 12:08:50 +00:00
|
|
|
void call(Label* L);
|
2009-10-06 13:11:05 +00:00
|
|
|
void call(Handle<Code> target, RelocInfo::Mode rmode);
|
2009-06-02 07:21:05 +00:00
|
|
|
|
|
|
|
// Call near absolute indirect, address in register
|
|
|
|
void call(Register adr);
|
2009-05-06 12:08:50 +00:00
|
|
|
|
2009-06-04 11:54:14 +00:00
|
|
|
// Call near indirect
|
|
|
|
void call(const Operand& operand);
|
|
|
|
|
2009-05-06 12:08:50 +00:00
|
|
|
// Jumps
|
2009-06-02 07:21:05 +00:00
|
|
|
// Jump short or near relative.
|
2009-10-06 13:11:05 +00:00
|
|
|
// Use a 32-bit signed displacement.
|
2009-05-06 12:08:50 +00:00
|
|
|
void jmp(Label* L); // unconditional jump to L
|
2009-10-06 13:11:05 +00:00
|
|
|
void jmp(Handle<Code> target, RelocInfo::Mode rmode);
|
2009-06-02 07:21:05 +00:00
|
|
|
|
|
|
|
// Jump near absolute indirect (r64)
|
|
|
|
void jmp(Register adr);
|
2009-05-06 12:08:50 +00:00
|
|
|
|
2009-08-19 10:18:30 +00:00
|
|
|
// Jump near absolute indirect (m64)
|
|
|
|
void jmp(const Operand& src);
|
|
|
|
|
2009-05-06 12:08:50 +00:00
|
|
|
// Conditional jumps
|
2009-05-26 12:32:09 +00:00
|
|
|
void j(Condition cc, Label* L);
|
2009-10-06 13:11:05 +00:00
|
|
|
void j(Condition cc, Handle<Code> target, RelocInfo::Mode rmode);
|
2009-05-06 12:08:50 +00:00
|
|
|
|
|
|
|
// Floating-point operations
|
|
|
|
void fld(int i);
|
|
|
|
|
|
|
|
void fld1();
|
|
|
|
void fldz();
|
|
|
|
|
|
|
|
void fld_s(const Operand& adr);
|
|
|
|
void fld_d(const Operand& adr);
|
|
|
|
|
|
|
|
void fstp_s(const Operand& adr);
|
|
|
|
void fstp_d(const Operand& adr);
|
2009-10-23 09:18:19 +00:00
|
|
|
void fstp(int index);
|
2009-05-06 12:08:50 +00:00
|
|
|
|
|
|
|
void fild_s(const Operand& adr);
|
|
|
|
void fild_d(const Operand& adr);
|
|
|
|
|
|
|
|
void fist_s(const Operand& adr);
|
|
|
|
|
|
|
|
void fistp_s(const Operand& adr);
|
|
|
|
void fistp_d(const Operand& adr);
|
|
|
|
|
|
|
|
void fisttp_s(const Operand& adr);
|
|
|
|
|
|
|
|
void fabs();
|
|
|
|
void fchs();
|
|
|
|
|
|
|
|
void fadd(int i);
|
|
|
|
void fsub(int i);
|
|
|
|
void fmul(int i);
|
|
|
|
void fdiv(int i);
|
|
|
|
|
|
|
|
void fisub_s(const Operand& adr);
|
|
|
|
|
|
|
|
void faddp(int i = 1);
|
|
|
|
void fsubp(int i = 1);
|
|
|
|
void fsubrp(int i = 1);
|
|
|
|
void fmulp(int i = 1);
|
|
|
|
void fdivp(int i = 1);
|
|
|
|
void fprem();
|
|
|
|
void fprem1();
|
|
|
|
|
|
|
|
void fxch(int i = 1);
|
|
|
|
void fincstp();
|
|
|
|
void ffree(int i = 0);
|
|
|
|
|
|
|
|
void ftst();
|
|
|
|
void fucomp(int i);
|
|
|
|
void fucompp();
|
2009-10-22 14:49:00 +00:00
|
|
|
void fucomi(int i);
|
2009-10-21 09:24:25 +00:00
|
|
|
void fucomip();
|
|
|
|
|
2009-05-06 12:08:50 +00:00
|
|
|
void fcompp();
|
|
|
|
void fnstsw_ax();
|
|
|
|
void fwait();
|
|
|
|
void fnclex();
|
|
|
|
|
2009-06-17 11:50:33 +00:00
|
|
|
void fsin();
|
|
|
|
void fcos();
|
|
|
|
|
2009-05-06 12:08:50 +00:00
|
|
|
void frndint();
|
|
|
|
|
2009-06-23 11:26:05 +00:00
|
|
|
void sahf();
|
|
|
|
|
|
|
|
// SSE2 instructions
|
|
|
|
void movsd(const Operand& dst, XMMRegister src);
|
2009-10-23 09:18:19 +00:00
|
|
|
void movsd(XMMRegister src, XMMRegister dst);
|
2009-06-23 11:26:05 +00:00
|
|
|
void movsd(XMMRegister src, const Operand& dst);
|
|
|
|
|
2009-05-06 12:08:50 +00:00
|
|
|
void cvttss2si(Register dst, const Operand& src);
|
|
|
|
void cvttsd2si(Register dst, const Operand& src);
|
|
|
|
|
2009-06-23 11:26:05 +00:00
|
|
|
void cvtlsi2sd(XMMRegister dst, const Operand& src);
|
|
|
|
void cvtlsi2sd(XMMRegister dst, Register src);
|
|
|
|
void cvtqsi2sd(XMMRegister dst, const Operand& src);
|
|
|
|
void cvtqsi2sd(XMMRegister dst, Register src);
|
2009-05-06 12:08:50 +00:00
|
|
|
|
|
|
|
void addsd(XMMRegister dst, XMMRegister src);
|
|
|
|
void subsd(XMMRegister dst, XMMRegister src);
|
|
|
|
void mulsd(XMMRegister dst, XMMRegister src);
|
|
|
|
void divsd(XMMRegister dst, XMMRegister src);
|
|
|
|
|
2009-06-23 11:26:05 +00:00
|
|
|
|
|
|
|
void emit_sse_operand(XMMRegister dst, XMMRegister src);
|
|
|
|
void emit_sse_operand(XMMRegister reg, const Operand& adr);
|
|
|
|
void emit_sse_operand(XMMRegister dst, Register src);
|
|
|
|
|
2009-05-06 12:08:50 +00:00
|
|
|
// Use either movsd or movlpd.
|
2009-06-10 15:53:46 +00:00
|
|
|
// void movdbl(XMMRegister dst, const Operand& src);
|
|
|
|
// void movdbl(const Operand& dst, XMMRegister src);
|
2009-05-06 12:08:50 +00:00
|
|
|
|
|
|
|
// Debugging
|
|
|
|
void Print();
|
|
|
|
|
|
|
|
// Check the code size generated from label to here.
|
|
|
|
int SizeOfCodeGeneratedSince(Label* l) { return pc_offset() - l->pos(); }
|
|
|
|
|
|
|
|
// Mark address of the ExitJSFrame code.
|
|
|
|
void RecordJSReturn();
|
|
|
|
|
|
|
|
// Record a comment relocation entry that can be used by a disassembler.
|
|
|
|
// Use --debug_code to enable.
|
|
|
|
void RecordComment(const char* msg);
|
|
|
|
|
|
|
|
void RecordPosition(int pos);
|
|
|
|
void RecordStatementPosition(int pos);
|
|
|
|
void WriteRecordedPositions();
|
|
|
|
|
2009-11-11 09:50:06 +00:00
|
|
|
int pc_offset() const { return static_cast<int>(pc_ - buffer_); }
|
2009-05-06 12:08:50 +00:00
|
|
|
int current_statement_position() const { return current_statement_position_; }
|
|
|
|
int current_position() const { return current_position_; }
|
|
|
|
|
|
|
|
// Check if there is less than kGap bytes available in the buffer.
|
|
|
|
// If this is the case, we need to grow the buffer before emitting
|
|
|
|
// an instruction or relocation information.
|
2009-09-10 12:55:27 +00:00
|
|
|
inline bool buffer_overflow() const {
|
|
|
|
return pc_ >= reloc_info_writer.pos() - kGap;
|
|
|
|
}
|
2009-05-06 12:08:50 +00:00
|
|
|
|
|
|
|
// Get the number of bytes available in the buffer.
|
2009-11-11 09:50:06 +00:00
|
|
|
inline int available_space() const {
|
|
|
|
return static_cast<int>(reloc_info_writer.pos() - pc_);
|
|
|
|
}
|
2009-05-06 12:08:50 +00:00
|
|
|
|
|
|
|
// Avoid overflows for displacements etc.
|
|
|
|
static const int kMaximalBufferSize = 512*MB;
|
|
|
|
static const int kMinimalBufferSize = 4*KB;
|
|
|
|
|
|
|
|
protected:
|
2009-06-10 15:53:46 +00:00
|
|
|
// void movsd(XMMRegister dst, const Operand& src);
|
|
|
|
// void movsd(const Operand& dst, XMMRegister src);
|
2009-05-06 12:08:50 +00:00
|
|
|
|
2009-06-10 15:53:46 +00:00
|
|
|
// void emit_sse_operand(XMMRegister reg, const Operand& adr);
|
|
|
|
// void emit_sse_operand(XMMRegister dst, XMMRegister src);
|
2009-05-06 12:08:50 +00:00
|
|
|
|
|
|
|
|
|
|
|
private:
|
|
|
|
byte* addr_at(int pos) { return buffer_ + pos; }
|
|
|
|
byte byte_at(int pos) { return buffer_[pos]; }
|
|
|
|
uint32_t long_at(int pos) {
|
|
|
|
return *reinterpret_cast<uint32_t*>(addr_at(pos));
|
|
|
|
}
|
|
|
|
void long_at_put(int pos, uint32_t x) {
|
|
|
|
*reinterpret_cast<uint32_t*>(addr_at(pos)) = x;
|
|
|
|
}
|
|
|
|
|
|
|
|
// code emission
|
|
|
|
void GrowBuffer();
|
2009-05-28 10:06:48 +00:00
|
|
|
|
|
|
|
void emit(byte x) { *pc_++ = x; }
|
2009-05-28 09:18:17 +00:00
|
|
|
inline void emitl(uint32_t x);
|
|
|
|
inline void emitq(uint64_t x, RelocInfo::Mode rmode);
|
2009-06-02 13:40:52 +00:00
|
|
|
inline void emitw(uint16_t x);
|
2009-10-06 13:11:05 +00:00
|
|
|
inline void emit_code_target(Handle<Code> target, RelocInfo::Mode rmode);
|
2009-05-28 09:18:17 +00:00
|
|
|
void emit(Immediate x) { emitl(x.value_); }
|
2009-05-06 12:08:50 +00:00
|
|
|
|
2009-05-22 07:53:28 +00:00
|
|
|
// Emits a REX prefix that encodes a 64-bit operand size and
|
|
|
|
// the top bit of both register codes.
|
2009-05-28 09:18:17 +00:00
|
|
|
// High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B.
|
|
|
|
// REX.W is set.
|
2009-05-22 07:53:28 +00:00
|
|
|
inline void emit_rex_64(Register reg, Register rm_reg);
|
2009-06-23 11:26:05 +00:00
|
|
|
inline void emit_rex_64(XMMRegister reg, Register rm_reg);
|
2009-05-22 07:53:28 +00:00
|
|
|
|
|
|
|
// Emits a REX prefix that encodes a 64-bit operand size and
|
|
|
|
// the top bit of the destination, index, and base register codes.
|
2009-05-28 09:18:17 +00:00
|
|
|
// The high bit of reg is used for REX.R, the high bit of op's base
|
|
|
|
// register is used for REX.B, and the high bit of op's index register
|
|
|
|
// is used for REX.X. REX.W is set.
|
2009-05-22 07:53:28 +00:00
|
|
|
inline void emit_rex_64(Register reg, const Operand& op);
|
2009-06-23 11:26:05 +00:00
|
|
|
inline void emit_rex_64(XMMRegister reg, const Operand& op);
|
2009-06-02 07:21:05 +00:00
|
|
|
|
|
|
|
// Emits a REX prefix that encodes a 64-bit operand size and
|
|
|
|
// the top bit of the register code.
|
|
|
|
// The high bit of register is used for REX.B.
|
|
|
|
// REX.W is set and REX.R and REX.X are clear.
|
|
|
|
inline void emit_rex_64(Register rm_reg);
|
|
|
|
|
|
|
|
// Emits a REX prefix that encodes a 64-bit operand size and
|
|
|
|
// the top bit of the index and base register codes.
|
|
|
|
// The high bit of op's base register is used for REX.B, and the high
|
|
|
|
// bit of op's index register is used for REX.X.
|
|
|
|
// REX.W is set and REX.R clear.
|
|
|
|
inline void emit_rex_64(const Operand& op);
|
2009-05-29 08:56:31 +00:00
|
|
|
|
2009-06-02 13:40:52 +00:00
|
|
|
// Emit a REX prefix that only sets REX.W to choose a 64-bit operand size.
|
|
|
|
void emit_rex_64() { emit(0x48); }
|
|
|
|
|
2009-05-29 08:56:31 +00:00
|
|
|
// High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B.
|
2009-06-02 07:21:05 +00:00
|
|
|
// REX.W is clear.
|
2009-05-29 08:56:31 +00:00
|
|
|
inline void emit_rex_32(Register reg, Register rm_reg);
|
|
|
|
|
|
|
|
// The high bit of reg is used for REX.R, the high bit of op's base
|
|
|
|
// register is used for REX.B, and the high bit of op's index register
|
|
|
|
// is used for REX.X. REX.W is cleared.
|
|
|
|
inline void emit_rex_32(Register reg, const Operand& op);
|
|
|
|
|
2009-06-03 10:30:50 +00:00
|
|
|
// High bit of rm_reg goes to REX.B.
|
|
|
|
// REX.W, REX.R and REX.X are clear.
|
|
|
|
inline void emit_rex_32(Register rm_reg);
|
|
|
|
|
|
|
|
// High bit of base goes to REX.B and high bit of index to REX.X.
|
|
|
|
// REX.W and REX.R are clear.
|
2009-06-03 13:30:31 +00:00
|
|
|
inline void emit_rex_32(const Operand& op);
|
2009-06-03 10:30:50 +00:00
|
|
|
|
2009-05-29 08:56:31 +00:00
|
|
|
// High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B.
|
|
|
|
// REX.W is cleared. If no REX bits are set, no byte is emitted.
|
|
|
|
inline void emit_optional_rex_32(Register reg, Register rm_reg);
|
|
|
|
|
|
|
|
// The high bit of reg is used for REX.R, the high bit of op's base
|
|
|
|
// register is used for REX.B, and the high bit of op's index register
|
|
|
|
// is used for REX.X. REX.W is cleared. If no REX bits are set, nothing
|
|
|
|
// is emitted.
|
|
|
|
inline void emit_optional_rex_32(Register reg, const Operand& op);
|
2009-05-22 07:53:28 +00:00
|
|
|
|
2009-06-23 11:26:05 +00:00
|
|
|
// As for emit_optional_rex_32(Register, Register), except that
|
|
|
|
// the registers are XMM registers.
|
|
|
|
inline void emit_optional_rex_32(XMMRegister reg, XMMRegister base);
|
|
|
|
|
|
|
|
// As for emit_optional_rex_32(Register, Register), except that
|
|
|
|
// the registers are XMM registers.
|
|
|
|
inline void emit_optional_rex_32(XMMRegister reg, Register base);
|
|
|
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// As for emit_optional_rex_32(Register, const Operand&), except that
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// the register is an XMM register.
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inline void emit_optional_rex_32(XMMRegister reg, const Operand& op);
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2009-06-03 10:30:50 +00:00
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// Optionally do as emit_rex_32(Register) if the register number has
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// the high bit set.
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inline void emit_optional_rex_32(Register rm_reg);
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// Optionally do as emit_rex_32(const Operand&) if the operand register
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// numbers have a high bit set.
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inline void emit_optional_rex_32(const Operand& op);
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2009-06-03 13:30:31 +00:00
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// Emit the ModR/M byte, and optionally the SIB byte and
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2009-05-28 10:06:48 +00:00
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// 1- or 4-byte offset for a memory operand. Also encodes
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2009-05-29 08:56:31 +00:00
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// the second operand of the operation, a register or operation
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2009-06-03 13:30:31 +00:00
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// subcode, into the reg field of the ModR/M byte.
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2009-06-02 07:21:05 +00:00
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void emit_operand(Register reg, const Operand& adr) {
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2009-06-22 08:17:44 +00:00
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emit_operand(reg.low_bits(), adr);
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2009-05-29 08:56:31 +00:00
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}
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2009-05-28 10:06:48 +00:00
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2009-06-03 13:30:31 +00:00
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// Emit the ModR/M byte, and optionally the SIB byte and
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2009-06-02 07:21:05 +00:00
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// 1- or 4-byte offset for a memory operand. Also used to encode
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2009-06-03 13:30:31 +00:00
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// a three-bit opcode extension into the ModR/M byte.
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2009-06-02 07:21:05 +00:00
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void emit_operand(int rm, const Operand& adr);
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2009-06-03 13:30:31 +00:00
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// Emit a ModR/M byte with registers coded in the reg and rm_reg fields.
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void emit_modrm(Register reg, Register rm_reg) {
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2009-06-22 08:17:44 +00:00
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emit(0xC0 | reg.low_bits() << 3 | rm_reg.low_bits());
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2009-06-03 13:30:31 +00:00
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}
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// Emit a ModR/M byte with an operation subcode in the reg field and
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// a register in the rm_reg field.
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void emit_modrm(int code, Register rm_reg) {
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2009-06-22 08:17:44 +00:00
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ASSERT(is_uint3(code));
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emit(0xC0 | code << 3 | rm_reg.low_bits());
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2009-06-03 13:30:31 +00:00
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}
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2009-05-06 12:08:50 +00:00
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// Emit the code-object-relative offset of the label's position
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inline void emit_code_relative_offset(Label* label);
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2009-05-28 10:06:48 +00:00
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// Emit machine code for one of the operations ADD, ADC, SUB, SBC,
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// AND, OR, XOR, or CMP. The encodings of these operations are all
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// similar, differing just in the opcode or in the reg field of the
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2009-06-03 13:30:31 +00:00
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// ModR/M byte.
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2009-08-14 11:24:32 +00:00
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void arithmetic_op_16(byte opcode, Register reg, Register rm_reg);
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void arithmetic_op_16(byte opcode, Register reg, const Operand& rm_reg);
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void arithmetic_op_32(byte opcode, Register reg, Register rm_reg);
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2009-07-21 13:30:46 +00:00
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void arithmetic_op_32(byte opcode, Register reg, const Operand& rm_reg);
|
2009-08-14 11:24:32 +00:00
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|
void arithmetic_op(byte opcode, Register reg, Register rm_reg);
|
2009-07-21 13:30:46 +00:00
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|
void arithmetic_op(byte opcode, Register reg, const Operand& rm_reg);
|
2009-05-28 09:18:17 +00:00
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void immediate_arithmetic_op(byte subcode, Register dst, Immediate src);
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void immediate_arithmetic_op(byte subcode, const Operand& dst, Immediate src);
|
2009-06-24 13:46:07 +00:00
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// Operate on a byte in memory or register.
|
2009-06-11 13:51:46 +00:00
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|
void immediate_arithmetic_op_8(byte subcode,
|
2009-08-14 11:24:32 +00:00
|
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|
Register dst,
|
2009-06-24 13:46:07 +00:00
|
|
|
Immediate src);
|
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|
|
void immediate_arithmetic_op_8(byte subcode,
|
2009-08-14 11:24:32 +00:00
|
|
|
const Operand& dst,
|
2009-06-24 13:46:07 +00:00
|
|
|
Immediate src);
|
2009-08-14 11:24:32 +00:00
|
|
|
// Operate on a word in memory or register.
|
|
|
|
void immediate_arithmetic_op_16(byte subcode,
|
|
|
|
Register dst,
|
|
|
|
Immediate src);
|
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|
|
void immediate_arithmetic_op_16(byte subcode,
|
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|
|
const Operand& dst,
|
|
|
|
Immediate src);
|
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|
|
// Operate on a 32-bit word in memory or register.
|
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|
|
void immediate_arithmetic_op_32(byte subcode,
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|
|
Register dst,
|
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|
|
Immediate src);
|
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|
|
void immediate_arithmetic_op_32(byte subcode,
|
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|
|
const Operand& dst,
|
|
|
|
Immediate src);
|
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|
|
|
2009-06-02 11:43:26 +00:00
|
|
|
// Emit machine code for a shift operation.
|
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|
|
void shift(Register dst, Immediate shift_amount, int subcode);
|
2009-07-09 08:00:12 +00:00
|
|
|
void shift_32(Register dst, Immediate shift_amount, int subcode);
|
2009-06-02 11:43:26 +00:00
|
|
|
// Shift dst by cl % 64 bits.
|
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|
|
void shift(Register dst, int subcode);
|
2009-06-17 11:50:33 +00:00
|
|
|
void shift_32(Register dst, int subcode);
|
2009-05-28 09:18:17 +00:00
|
|
|
|
2009-06-17 11:50:33 +00:00
|
|
|
void emit_farith(int b1, int b2, int i);
|
2009-05-06 12:08:50 +00:00
|
|
|
|
|
|
|
// labels
|
2009-06-10 15:53:46 +00:00
|
|
|
// void print(Label* L);
|
2009-05-06 12:08:50 +00:00
|
|
|
void bind_to(Label* L, int pos);
|
|
|
|
void link_to(Label* L, Label* appendix);
|
|
|
|
|
|
|
|
// record reloc info for current pc_
|
2009-05-29 08:56:31 +00:00
|
|
|
void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0);
|
2009-05-06 12:08:50 +00:00
|
|
|
|
|
|
|
friend class CodePatcher;
|
|
|
|
friend class EnsureSpace;
|
2009-08-14 11:24:32 +00:00
|
|
|
friend class RegExpMacroAssemblerX64;
|
2009-05-06 12:08:50 +00:00
|
|
|
|
|
|
|
// Code buffer:
|
|
|
|
// The buffer into which code and relocation info are generated.
|
|
|
|
byte* buffer_;
|
|
|
|
int buffer_size_;
|
|
|
|
// True if the assembler owns the buffer, false if buffer is external.
|
|
|
|
bool own_buffer_;
|
2009-05-20 12:17:23 +00:00
|
|
|
// A previously allocated buffer of kMinimalBufferSize bytes, or NULL.
|
|
|
|
static byte* spare_buffer_;
|
2009-05-06 12:08:50 +00:00
|
|
|
|
|
|
|
// code generation
|
|
|
|
byte* pc_; // the program counter; moves forward
|
|
|
|
RelocInfoWriter reloc_info_writer;
|
|
|
|
|
2009-10-06 13:11:05 +00:00
|
|
|
List< Handle<Code> > code_targets_;
|
2009-05-06 12:08:50 +00:00
|
|
|
// push-pop elimination
|
|
|
|
byte* last_pc_;
|
|
|
|
|
|
|
|
// source position information
|
|
|
|
int current_statement_position_;
|
|
|
|
int current_position_;
|
|
|
|
int written_statement_position_;
|
|
|
|
int written_position_;
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
// Helper class that ensures that there is enough space for generating
|
|
|
|
// instructions and relocation information. The constructor makes
|
|
|
|
// sure that there is enough space and (in debug mode) the destructor
|
|
|
|
// checks that we did not generate too much.
|
|
|
|
class EnsureSpace BASE_EMBEDDED {
|
|
|
|
public:
|
|
|
|
explicit EnsureSpace(Assembler* assembler) : assembler_(assembler) {
|
2009-09-10 12:55:27 +00:00
|
|
|
if (assembler_->buffer_overflow()) assembler_->GrowBuffer();
|
2009-05-06 12:08:50 +00:00
|
|
|
#ifdef DEBUG
|
|
|
|
space_before_ = assembler_->available_space();
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef DEBUG
|
|
|
|
~EnsureSpace() {
|
|
|
|
int bytes_generated = space_before_ - assembler_->available_space();
|
|
|
|
ASSERT(bytes_generated < assembler_->kGap);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
private:
|
|
|
|
Assembler* assembler_;
|
|
|
|
#ifdef DEBUG
|
|
|
|
int space_before_;
|
|
|
|
#endif
|
|
|
|
};
|
|
|
|
|
2009-05-05 14:39:05 +00:00
|
|
|
} } // namespace v8::internal
|
|
|
|
|
|
|
|
#endif // V8_X64_ASSEMBLER_X64_H_
|